SBOS875C August   2017  – February 2023 THS3491

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Bare Die Information
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics: VS = ±15 V
    6. 8.6 Electrical Characteristics: VS = ±7.5 V
    7. 8.7 Typical Characteristics: ±15 V
    8. 8.8 Typical Characteristics: ±7.5 V
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Power-Down (PD) Pin
      2. 9.3.2 Power-Down Reference (REF) Pin
      3. 9.3.3 Internal Junction Temperature Sense (TJ_SENSE) Pin
    4. 9.4 Device Functional Modes
      1. 9.4.1 Wideband Noninverting Operation
      2. 9.4.2 Wideband, Inverting Operation
      3. 9.4.3 Single-Supply Operation
      4. 9.4.4 Maximum Recommended Output Voltage
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Driving Capacitive Loads
      2. 10.1.2 Video Distribution
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
        1. 10.4.1.1 PowerPAD™ Integrated Circuit Package Design Considerations (DDA Package Only)
          1. 10.4.1.1.1 PowerPAD™ Integrated Circuit Package Layout Considerations
          2. 10.4.1.1.2 Power Dissipation and Thermal Considerations
      2. 10.4.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.3.2 Power-Down Reference (REF) Pin

In addition to the power-down pin, the DDA package features a reference pin (REF) that allows control over the enable or disable power-down voltage levels applied to the PD pin. This reference pin is explicitly pinned out on the DDA package as the REF pin. However, on the RGT package, the reference pin refers to pin 5 (GND), which must be connected to GND. In most split-supply applications, the reference pin is connected to ground. In either case, be aware of voltage-level thresholds that apply to the power-down pin. #GUID-0E7ED393-9AFE-4C86-AF30-D284F86D3F4D/SLOS4237489 provides examples and shows the relationship between the reference voltage and the power-down thresholds. In #GUID-0E7ED393-9AFE-4C86-AF30-D284F86D3F4D/SLOS4237489, the threshold levels are derived by the conditions that follow:

  • PD ≤ REF + 0.8 V (Disable)
  • PD  ≥ REF + 1.5 V (Enable)
where the usable range at the REF pin is:
  • VS– ≤ VREF ≤  (VS+  – 5 V)

Table 9-1 Example Power-Down Threshold Voltage Levels
SUPPLY
VOLTAGE (V)		REFERENCE PIN
VOLTAGE (V)		ENABLE
LEVEL (V)		DISABLE
LEVEL (V)
±15, ±7, 3001.50.8
±1523.52.8
±15–2–0.5–1.2
±712.51.8
±7–10.5–0.2
301516.515.8
1478.57.8

The recommended operating mode is to tie the REF pin to ground for single and split-supply operations, which sets the enable and disable thresholds to 1.5 V and 0.8 V, respectively.

The REF pin must be tied to a valid potential within the recommended operating range of (–VS ≤ V(REF) ≤ +VS – 5 V). Although the PD pin can be floated, TI does not recommend floating the PD pin in case stray signals couple into the pin and cause unintended turnon or turnoff device behavior. However, if the PD pin is left unterminated, the PD pin floats to 2 V below the positive rail and the device remains enabled. As a result, the THS3491 DDA package is a drop-in replacement for the THS3091 DDA pinout if the REF pin (pin 1) is tied to a valid potential. If balanced, split supplies are used (±VS) and the REF and PD pins are grounded, the device is disabled.