SBOS875C August   2017  – February 2023 THS3491

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Bare Die Information
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics: VS = ±15 V
    6. 8.6 Electrical Characteristics: VS = ±7.5 V
    7. 8.7 Typical Characteristics: ±15 V
    8. 8.8 Typical Characteristics: ±7.5 V
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Power-Down (PD) Pin
      2. 9.3.2 Power-Down Reference (REF) Pin
      3. 9.3.3 Internal Junction Temperature Sense (TJ_SENSE) Pin
    4. 9.4 Device Functional Modes
      1. 9.4.1 Wideband Noninverting Operation
      2. 9.4.2 Wideband, Inverting Operation
      3. 9.4.3 Single-Supply Operation
      4. 9.4.4 Maximum Recommended Output Voltage
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Driving Capacitive Loads
      2. 10.1.2 Video Distribution
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
        1. 10.4.1.1 PowerPAD™ Integrated Circuit Package Design Considerations (DDA Package Only)
          1. 10.4.1.1.1 PowerPAD™ Integrated Circuit Package Layout Considerations
          2. 10.4.1.1.2 Power Dissipation and Thermal Considerations
      2. 10.4.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
10.4.1.1.1 PowerPAD™ Integrated Circuit Package Layout Considerations

The DDA package top-side etch and via pattern is shown in #SLOS420FIG2811.

GUID-F150A1CB-7B02-48E4-9AFF-D19124004AE8-low.gifFigure 10-11 DDA PowerPAD™ Integrated Circuit Package PCB Etch and Via Pattern
  1. Use etch for the leads and the thermal pad.
  2. Place 13 vias in the thermal pad area. These vias must be 0.01 inch (0.254 mm) in diameter. Keep the vias small so that solder wicking through the vias is not a problem during reflow.
  3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area, and help dissipate the heat generated by the THS3491 device. These additional vias may be larger than the 0.01-inch (0.254 mm) diameter vias directly under the thermal pad because they are not in the area that requires soldering. As a result, wicking is not a problem.
  4. Connect all vias to the internal ground plane. The PowerPAD integrated circuit package is electrically isolated from the silicon and all leads. Connecting the PowerPAD integrated circuit package to any potential voltage such as –VS is acceptable because there is no electrical connection to the silicon.
  5. When connecting these vias to the ground plane, do not use the typical web or spoke through connection methodology. Web and spoke connections have a high thermal resistance that slows the heat transfer during soldering . Avoiding these connection methods makes the soldering of vias that have plane connections easier. In this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the vias under the THS3491 PowerPAD integrated circuit package must connect to the internal ground plane with a complete connection around the entire circumference of the plated-through hole.
  6. The top-side solder mask must leave the pins of the package and the thermal pad area with the 13 vias exposed.
  7. Apply solder paste to the exposed thermal pad area and all of the device pins.
  8. With these preparatory steps in place, the device is placed in position and run through the solder reflow operation as any standard surface-mount component. This results in a device that is properly installed.