SBOS875C August   2017  – February 2023 THS3491

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Bare Die Information
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics: VS = ±15 V
    6. 8.6 Electrical Characteristics: VS = ±7.5 V
    7. 8.7 Typical Characteristics: ±15 V
    8. 8.8 Typical Characteristics: ±7.5 V
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Power-Down (PD) Pin
      2. 9.3.2 Power-Down Reference (REF) Pin
      3. 9.3.3 Internal Junction Temperature Sense (TJ_SENSE) Pin
    4. 9.4 Device Functional Modes
      1. 9.4.1 Wideband Noninverting Operation
      2. 9.4.2 Wideband, Inverting Operation
      3. 9.4.3 Single-Supply Operation
      4. 9.4.4 Maximum Recommended Output Voltage
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Driving Capacitive Loads
      2. 10.1.2 Video Distribution
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
        1. 10.4.1.1 PowerPAD™ Integrated Circuit Package Design Considerations (DDA Package Only)
          1. 10.4.1.1.1 PowerPAD™ Integrated Circuit Package Layout Considerations
          2. 10.4.1.1.2 Power Dissipation and Thermal Considerations
      2. 10.4.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10.4.1 Layout Guidelines

Achieving optimum performance with a high-frequency amplifier such as the THS3491 requires careful attention to board layout parasitic and external component types.

Recommendations that optimize performance include:

  • Minimize parasitic capacitance to any AC ground for all of the signal I/O pins. Parasitic capacitance on the output and input pins can cause instability. To reduce unwanted capacitance, a window around the signal I/O pins must be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes must be unbroken elsewhere on the board.
  • Minimize the distance (< 0.25 of an inch [6.35 mm] from the power supply pins to high-frequency 0.1-μF and 100-pF decoupling capacitors. At the device pins, the ground and power plane layout must not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The power supply connections must always be decoupled with these capacitors Use larger tantalum decoupling capacitors (with a value of 6.8 µF or more) that are effective at lower frequencies on the main supply pins. These can be placed further from the device and can be shared among several devices in the same area of the printed circuit board (PCB).
  • Careful selection and placement of external components preserve the high-frequency performance of the THS3491. Resistors must be a low reactance type. Surface-mount resistors work best and allow a tighter overall layout. Keep leads and PCB trace length as short as possible. Never use wire-bound type resistors in a high-frequency application. Because the output pin and inverting input pins are the most sensitive to parasitic capacitance, always position the feedback and series output resistors, if any, as close to the inverting input pins and output pins as possible, respectively. Place other network components such as input termination resistors close to the gain setting resistors. Even with a low parasitic capacitance shunting the external resistors, excessively high resistor values create significant time constants constraints? that can degrade performance. Good axial metal film or surface-mount resistors feature approximately 0.2 pF capacitance in shunt with the resistor. For resistor values greater than 2 kΩ, this parasitic capacitance adds a pole or a zero that can effect circuit operation. Keep resistor values as low as possible and consistent with load-driving considerations.
  • Make connections to other wideband devices on the board with short direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Use relatively wide traces of 0.05 inch to 0.1 inch (1.3 mm to 2.54 mm), preferably with open ground and power planes around the traces. Estimate the total capacitive load and determine if isolation resistors on the outputs are required. Low parasitic capacitive loads ( less than 4 pF) may not require series resistance because the THS3491 is nominally compensated to operate with a 2-pF parasitic load. Higher parasitic capacitive loads without a series resistance are allowed as the signal gain increases (increasing the unloaded phase margin). If a long trace is required and the 6-dB signal loss intrinsic to a twice-terminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques).
  • A 50-Ω environment is not required onboard, and a higher impedance environment improves distortion as shown in the distortion versus load plots; see GUID-E5F9035E-1746-4A47-8531-1DFCA205BA30.html#X112 and GUID-E5F9035E-1746-4A47-8531-1DFCA205BA30.html#SBOS875_THS3491878. With a characteristic board trace impedance based on board material and trace dimensions, a matching series resistor into the trace from the output of the THS3491 is used. A terminating shunt resistor at the input of the destination device is also used. The terminating impedance is the parallel combination of the shunt resistor and the input impedance of the destination device. This total effective impedance must be set to match the trace impedance.
    If the 6-dB attenuation of a twice-terminated transmission line is unacceptable, a long trace can be series terminated at the source end only. Treat the trace as a capacitive load in this case. This termination does not preserve signal integrity as well as a twice-terminated line. If the input impedance of the destination device is low, there is some signal attenuation because of the voltage divider formed by the series output into the terminating impedance.
  • Do not socket a high-speed device like the THS3491. The socket introduces additional lead lengths and pin-to-pin capacitance, which can create a troublesome parasitic network. This can make it achieving a smooth, stable frequency response impossible. Obtain better results by soldering the THS3491 devices directly onto the board.