SLOS265F August   1999  – July 2024 THS4021 , THS4022

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information - THS4021
    5. 5.5 Thermal Information - THS4022
    6. 5.6 Electrical Characteristics - THS4021D and THS4022DGN
    7. 5.7 Electrical Characteristics - THS4021DGN
    8. 5.8 Typical Characteristics: THS4021D and THS4022DGN
    9. 5.9 Typical Characteristics: THS4021DGN
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Offset Nulling
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Driving a Capacitive Load
      2. 7.1.2 General Configuration
    2. 7.2 Power Supply Recommendations
    3. 7.3 Layout
      1. 7.3.1 Layout Guidelines
        1. 7.3.1.1 General PowerPAD™ Integrated Circuit Package Design Considerations
      2. 7.3.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
  • DGN|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.8 Typical Characteristics: THS4021D and THS4022DGN

at TA = 25°C, VCC = ±15 V, gain = +10 V/V, RL = 150 Ω, and RF = 220 Ω (unless otherwise noted)

THS4021 THS4022 Frequency Response vs Feedback Resistance
VCC = ±15 V, VOUT = 100 mVPP
Figure 5-1 Frequency Response vs Feedback Resistance
THS4021 THS4022 Frequency Response vs Gain
VCC = ±15 V, VOUT = 100 mVPP
Figure 5-3 Frequency Response vs Gain
THS4021 THS4022 Large-Signal Frequency Response
VCC = ±15 V
Figure 5-5 Large-Signal Frequency Response
THS4021 THS4022 Closed-Loop Output Impedance
 
Figure 5-7 Closed-Loop Output Impedance
THS4021 THS4022 Power-Supply Rejection Ratio vs Frequency
 
Figure 5-9 Power-Supply Rejection Ratio vs Frequency
THS4021 THS4022 Input-Referred Voltage Noise vs Frequency
VCC = ±15 V
Figure 5-11 Input-Referred Voltage Noise vs Frequency
THS4021 THS4022 Harmonic Distortion vs Frequency
VCC = ±15 V, RL = 1 kΩ, VOUT = 2 VPP
Figure 5-13 Harmonic Distortion vs Frequency
THS4021 THS4022 Harmonic Distortion vs Frequency
VCC = ±15 V, RL = 150 Ω, VOUT = 2 VPP
Figure 5-15 Harmonic Distortion vs Frequency
THS4021 THS4022 Harmonic Distortion vs Peak‑to‑Peak Output Voltage
VCC = ±15 V, RL = 1 kΩ, f = 1 MHz
Figure 5-17 Harmonic Distortion vs Peak‑to‑Peak Output Voltage
THS4021 THS4022 Total Harmonic Distortion vs Frequency
VCC = ±15 V, VOUT = 2 VPP
Figure 5-19 Total Harmonic Distortion vs Frequency
THS4021 THS4022 1-V Step Response
 
Figure 5-21 1-V Step Response
THS4021 THS4022 10-V Step Response
VCC = ±15 V
Figure 5-23 10-V Step Response
THS4021 THS4022 Voltage Offset Distribution
μ = 0.212, σ = 0.0903
Figure 5-25 Voltage Offset Distribution
THS4021 THS4022 Input Offset Current vs Ambient Temperature
μ = 0.164, σ = 0.0395
Figure 5-27 Input Offset Current vs Ambient Temperature
THS4021 THS4022 Maximum Output Voltage Swing vs Ambient Temperature
 
Figure 5-29 Maximum Output Voltage Swing vs Ambient Temperature
THS4021 THS4022 Supply Current vs Ambient Temperature
 
Figure 5-31 Supply Current vs Ambient Temperature
THS4021 THS4022 Frequency Response vs Feedback Resistance
VCC = ±5 V, VOUT = 100 mVPP
Figure 5-2 Frequency Response vs Feedback Resistance
THS4021 THS4022 Frequency Response vs Gain
VCC = ±5 V, VOUT = 100 mVPP
Figure 5-4 Frequency Response vs Gain
THS4021 THS4022 Large-Signal Frequency Response
VCC = ±5 V
Figure 5-6 Large-Signal Frequency Response
THS4021 THS4022 Open-loop Gain and Phase Response
 
Figure 5-8 Open-loop Gain and Phase Response
THS4021 THS4022 Common-Mode Rejection Ratio vs Frequency
 
Figure 5-10 Common-Mode Rejection Ratio vs Frequency
THS4021 THS4022 Input-Referred Current Noise vs Frequency
VCC = ±15 V, RL = 150 Ω, VOUT = 2 VPP
Figure 5-12 Input-Referred Current Noise vs Frequency
THS4021 THS4022 Harmonic Distortion vs Frequency
VCC = ±5 V, RL = 1 kΩ, VOUT = 2 VPP
Figure 5-14 Harmonic Distortion vs Frequency
THS4021 THS4022 Harmonic Distortion vs Frequency
VCC = ±5 V, RL = 150 Ω, VOUT = 2 VPP
Figure 5-16 Harmonic Distortion vs Frequency
THS4021 THS4022 Harmonic Distortion vs Peak‑to‑Peak Output Voltage
VCC = ±15 V, RL = 150 Ω, f = 1 MHz
Figure 5-18 Harmonic Distortion vs Peak‑to‑Peak Output Voltage
THS4021 THS4022 Crosstalk vs Frequency
 
Figure 5-20 Crosstalk vs Frequency
THS4021 THS4022 5-V Step Response
VCC = ±5 V
Figure 5-22 5-V Step Response
THS4021 THS4022 Input Offset Voltage vs Ambient Temperature
3 typical units
Figure 5-24 Input Offset Voltage vs Ambient Temperature
THS4021 THS4022 Input Offset Current vs Ambient Temperature
3 typical units
Figure 5-26 Input Offset Current vs Ambient Temperature
THS4021 THS4022 Offset Voltage vs Output Voltage
 
Figure 5-28 Offset Voltage vs Output Voltage
THS4021 THS4022 Output Swing vs Load Current
 
Figure 5-30 Output Swing vs Load Current