SLOS224L June   1999  – July 2024 THS4031 , THS4032

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information - THS4031
    5. 5.5 Thermal Information - THS4032
    6. 5.6 Electrical Characteristics - RL = 150Ω
    7. 5.7 Electrical Characteristics - RL = 1kΩ
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Offset Nulling
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Driving a Capacitive Load
      2. 7.1.2 Low-Pass Filter Configurations
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Multiplexer Selection
        2. 7.2.2.2 Signal Source
        3. 7.2.2.3 Driving Amplifier
          1. 7.2.2.3.1 Driving Amplifier Bandwidth Restriction
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 General PowerPAD™ Integrated Circuit Package Design Considerations
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
  • DGN|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.8 Typical Characteristics

at TA = 25°C, VCC = ±15V, gain = +1V/V, RL = 150Ω, and RF = 300Ω (unless otherwise noted)

THS4031 THS4032 Frequency Response vs Feedback Resistance
VCC = ±15V, RL = 150Ω, VOUT = 200mVPP
Figure 5-1 Frequency Response vs Feedback Resistance
THS4031 THS4032 Frequency Response vs Feedback Resistance
VCC = ±5V, RL = 150Ω, VOUT = 200mVPP
Figure 5-3 Frequency Response vs Feedback Resistance
THS4031 THS4032 Frequency Response vs Feedback Resistance
Gain = +2V/V, VOUT = 400mVPP
Figure 5-5 Frequency Response vs Feedback Resistance
THS4031 THS4032 Large-Signal Frequency Response
VCC = ±15V
Figure 5-7 Large-Signal Frequency Response
THS4031 THS4032 Closed-Loop Output Impedance
 
Figure 5-9 Closed-Loop Output Impedance
THS4031 THS4032 Power-Supply Rejection Ratio vs Frequency
 
Figure 5-11 Power-Supply Rejection Ratio vs Frequency
THS4031 THS4032 Input-Referred Voltage Noise vs Frequency
 
Figure 5-13 Input-Referred Voltage Noise vs Frequency
THS4031 THS4032 THS4031 Harmonic Distortion vs Frequency
VCC = ±15V, gain = +2V/V, RL = 1kΩ, VOUT = 2VPP
Figure 5-15 THS4031 Harmonic Distortion vs Frequency
THS4031 THS4032 THS4031 Harmonic Distortion vs Frequency
VCC = ±15V, gain = +2V/V, RL = 150Ω, VOUT = 2VPP
Figure 5-17 THS4031 Harmonic Distortion vs Frequency
THS4031 THS4032 Harmonic Distortion vs Peak‑to‑Peak Output Voltage
VCC = ±15V, gain = +5V/V, RL = 1kΩ, f = 1MHz
Figure 5-19 Harmonic Distortion vs Peak‑to‑Peak Output Voltage
THS4031 THS4032 THS4032 Crosstalk vs Frequency
VCC = ±15V, gain = +2V/V
Figure 5-21 THS4032 Crosstalk vs Frequency
THS4031 THS4032 4V Step Response
VCC = ±5V, gain = –1V/V, RF = 430Ω
Figure 5-23 4V Step Response
THS4031 THS4032 Input Offset Voltage vs Ambient Temperature
3 typical units
Figure 5-25 Input Offset Voltage vs Ambient Temperature
THS4031 THS4032 Input Offset Current vs Ambient Temperature
3 typical units
Figure 5-27 Input Offset Current vs Ambient Temperature
THS4031 THS4032 Offset Voltage vs Output Voltage
 
Figure 5-29 Offset Voltage vs Output Voltage
THS4031 THS4032 Output Swing vs Load Current
 
Figure 5-31 Output Swing vs Load Current
THS4031 THS4032 Frequency Response vs Feedback Resistance
VCC = ±15V, RL = 1kΩ, VOUT = 200mVPP
Figure 5-2 Frequency Response vs Feedback Resistance
THS4031 THS4032 Frequency Response vs Feedback Resistance
VCC = ±5V, RL = 1kΩ, VOUT = 200mVPP
Figure 5-4 Frequency Response vs Feedback Resistance
THS4031 THS4032 Frequency Response vs Feedback Resistance
VCC = ±5V, gain = +2V/V, VOUT = 400mVPP
Figure 5-6 Frequency Response vs Feedback Resistance
THS4031 THS4032 Large-Signal Frequency Response
VCC = ±5V
Figure 5-8 Large-Signal Frequency Response
THS4031 THS4032 Open-Loop Gain and Phase Response
 
Figure 5-10 Open-Loop Gain and Phase Response
THS4031 THS4032 Common-Mode Rejection Ratio vs Frequency
 
Figure 5-12 Common-Mode Rejection Ratio vs Frequency
THS4031 THS4032 Input-Referred Current Noise vs Frequency
 
Figure 5-14 Input-Referred Current Noise vs Frequency
THS4031 THS4032 THS4031 Harmonic Distortion vs Frequency
VCC = ±5V, gain = +2V/V, RL = 1kΩ, VOUT = 2VPP
Figure 5-16 THS4031 Harmonic Distortion vs Frequency
THS4031 THS4032 THS4031 Harmonic Distortion vs Frequency
VCC = ±5V, gain = +2V/V, RL = 150Ω, VOUT = 2VPP
Figure 5-18 THS4031 Harmonic Distortion vs Frequency
THS4031 THS4032 Harmonic Distortion vs Peak‑to‑Peak Output Voltage
VCC = ±15V, gain = +5V/V, RL = 150Ω, f = 1MHz
Figure 5-20 Harmonic Distortion vs Peak‑to‑Peak Output Voltage
THS4031 THS4032 1V Step Response
Gain = +2V/V
Figure 5-22 1V Step Response
THS4031 THS4032 20V Step Response
Gain = +2V/V
Figure 5-24 20V Step Response
THS4031 THS4032 Voltage Offset Distribution
μ = 0.209, σ = 0.0911
Figure 5-26 Voltage Offset Distribution
THS4031 THS4032 Input Offset Current vs Ambient Temperature
μ = 0.0179, σ = 0.0317
Figure 5-28 Input Offset Current vs Ambient Temperature
THS4031 THS4032 Maximum Output Voltage Swing vs Ambient Temperature
 
Figure 5-30 Maximum Output Voltage Swing vs Ambient Temperature
THS4031 THS4032 Supply Current vs Ambient Temperature
 
Figure 5-32 Supply Current vs Ambient Temperature