SLOSE89A November   2021  – March 2022 THS4541-DIE

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Bare Die Information
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Recommended Operating Conditions
    3. 7.3 Electrical Characteristics: (Vs+) - Vs- = 5 V
    4. 7.4 Typical Characteristics 5-V Single Supply
    5. 7.5 Typical Characteristics: 3-V to 5-V Supply Range
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 Terminology and Application Assumptions
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Differential I/O
      2. 8.3.2 Power-Down Control Pin (PD)
        1. 8.3.2.1 Operating the Power Shutdown Feature
      3. 8.3.3 Input Overdrive Operation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation from Single-Ended Sources to Differential Outputs
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Interfacing to High-Performance ADCs
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
        1. 12.1.1.1 TINA Simulation Model Features
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
  • Y|0
Thermal pad, mechanical data (Package|Pins)
Orderable Information

12.1.1.1 TINA Simulation Model Features

The device model is available as part of the TINA model library. The model includes numerous features intended to speed designer progress over a wide range of application requirements. The following list shows the performance parameters included in the model:

  • For the small-signal response shape with any external circuit:
    • Differential open loop gain and phase
    • Parasitic input capacitance
    • Open-loop differential output impedance
  • For noise simulations:
    • Input differential spot voltage noise and a 100-kHz 1/f corner
    • Input current noise on each input with a 1-MHz 1/f corner
  • For time-domain, step-response simulations:
    • Differential slew rate
    • I/O headroom models to predict clipping
    • Fine-scale, DC precision terms:
      • PSRR
      • CMRR

The typical characterization curves show more detail than the macromodels can provide; some of those unmodeled features include:

  • Harmonic distortion
  • Temperature drift in DC error terms (VIO and IOS)