SLOSE89A November   2021  – March 2022 THS4541-DIE

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Bare Die Information
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Recommended Operating Conditions
    3. 7.3 Electrical Characteristics: (Vs+) - Vs- = 5 V
    4. 7.4 Typical Characteristics 5-V Single Supply
    5. 7.5 Typical Characteristics: 3-V to 5-V Supply Range
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 Terminology and Application Assumptions
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Differential I/O
      2. 8.3.2 Power-Down Control Pin (PD)
        1. 8.3.2.1 Operating the Power Shutdown Feature
      3. 8.3.3 Input Overdrive Operation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation from Single-Ended Sources to Differential Outputs
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Interfacing to High-Performance ADCs
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
        1. 12.1.1.1 TINA Simulation Model Features
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
  • Y|0
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3 Electrical Characteristics: (Vs+) - Vs- = 5 V

At TA ≈ 25°C, Vocm = open (defaults midsupply), VOUT= 2 VPP, Rf = 402 Ω, Rload = 499 Ω, 50-Ω input match, G = 2 V/V, single-ended input, differential output, and PD = +Vs, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AC PERFORMANCE
Small-signal bandwidth Vout = 100 mVPP, G = 1 620 MHz
Vout = 100 mVPP, G = 2 500 MHz
Vout = 100 mVPP, G = 5 210 MHz
Vout = 100 mVPP, G = 10 125 MHz
Gain-bandwidth product Vout = 100 mVPP, G = 20 850 MHz
Large-signal bandwidth Vout = 2 VPP, G = 2 340 MHz
Bandwidth for 0.1-dB flatness Vout = 2 VPP, G = 2 100 MHz
Slew rate(1) Vout = 2-VPP, FPBW 1500 V/µs
Rise/fall time Vout = 2-V step, G = 2 input ≤ 0.3 ns tr 1.4 ns
Settling time To 1%, Vout = 2-V step, tr = 2 ns, G = 2 4 ns
To 0.1%,Vout = 2-V step, tr = 2 ns, G = 2 8 ns
Overshoot and undershoot Vout = 2-V step G = 2, input ≤ 0.3 ns tr  10%
100-kHz harmonic distortion Vout = 2 VPP, G = 2, HD2 –140 dBc
Vout = 2 VPP, G = 2, HD3 –140 dBc
10-MHz harmonic distortion Vout = 2 VPP, G = 2, HD2 –95 dBc
Vout = 2 VPP, G = 2, HD3 –90 dBc
2nd-order intermodulation distortion f = 10 MHz, 100-kHz tone spacing, Vout envelope = 2 VPP (1 VPP per tone –90 dBc
3rd-order intermodulation distortion –85 dBc
Input voltage noise f > 100 kHz 2.2 nV/√Hz
Input current noise f > 1 MHz 1.9 pA/√Hz
Overdrive recovery time 2x output overdrive, either polarity 20 ns
Closed-loop output impedance f = 10 MHz (differential) 0.1 Ω
DC PERFORMANCE
AOL Open-loop voltage gain 100 119 dB
Input-referred offset voltage –900 ±100 900 µV
Input offset voltage drift(2) TA = –40°C to +125°C ±0.5 µV/°C
Input bias current (positive out of node) 10 15 µA
Input bias current drift(2) TA = –40°C to +125°C 6 nA/°C
Input offset current –650 ±150 650 nA
Input offset current drift(2) TA = –40°C to +125°C ±0.3 nA/°C
INPUT
Common-mode input low < 3-dB degradation in CMRR from midsupply (Vs–) – 0.2 (Vs–) – 0.1 V
Common-mode input high (Vs+) – 1.3 (Vs+) –1.2 V
Common-mode rejection ratio Input pins at ((Vs+) – Vs–) / 2 85 100 dB
Input impedance differential mode 110 || 0.85 kΩ || pF
OUTPUT
Output voltage low (Vs–) + 0.2 (Vs–) + 0.25 V
Output voltage high (Vs+) – 0.25 (Vs+) – 0.2 V
Output current drive ±75 ±100 mA
POWER SUPPLY
Specified operating voltage 2.7 5 5.4 V
Quiescent operating current Vs+ = 5 V Vs+ = 5 V 9.7 10.1 10.5 mA
±PSRR Power-supply rejection ratio Either supply pin to differential Vout 85 100 dB
POWER DOWN
Enable voltage threshold (Vs–) + 1.7 V
Disable voltage threshold (Vs–) + 0.7 V
Disable pin bias current PD = Vs– → Vs+ 20 50 nA
Power-down quiescent current PD = (Vs–) + 0.7 V 6 30 µA
PD = Vs– 2 8 µA
Turnon-time delay Time from PD = low to Vout = 90% of final value 100 ns
Turnoff time delay 60 ns
OUTPUT COMMON-MODE VOLTAGE CONTROL(3)
Small-signal bandwidth Vocm = 100 mVPP 150 MHz
Slew rate(1) Vocm = 2-V step 400 V/µs
Gain 0.975 0.982 0.995 V/V
Input bias current Considered positive out of node –0.8 0.1 0.8 µA
Input impedance Vocm input driven to ((Vs+) – Vs–) / 2 47 || 1.2 kΩ || pF
Default voltage offset from ((Vs+) – Vs–) / 2 Vocm pin open –40 ±8 40 mV
CM Vos Common-mode offset voltage Vocm input driven to ((Vs+) – Vs–) / 2 –5 ±2 5 mV
Common-mode offset voltage drift(2) ±4 mV/°C
Common-mode loop supply headroom to negative supply < ±12-mV shift from midsupply CM Vos 0.88 V
Common-mode loop supply headroom to positive supply 1.1 V
(1) This slew rate is the average of the rising and falling time estimated from the large-signal bandwidth as: (VP / √2) · 2π · f–3dB.
(2) Input offset voltage drift, input bias current drift, input offset current drift, and Vocm drift are average values calculated by taking data at the at the maximum-range ambient-temperature end-points, computing the difference, and dividing by the temperature range.
(3) Specifications are from the input Vocm pin to the differential output average voltage.