SLOS375B August   2014  – February 2024 THS4541

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: (Vs+) – Vs– = 5 V
    6. 6.6 Electrical Characteristics: (Vs+) – Vs– = 3 V
    7. 6.7 Typical Characteristics 5-V Single Supply
    8. 6.8 Typical Characteristics: 3-V Single Supply
    9. 6.9 Typical Characteristics: 3-V to 5-V Supply Range
  8. 7 Parameter Measurement Information
    1. 7.1 Example Characterization Circuits
    2. 7.2 Frequency-Response Shape Factors
    3. 7.3 I/O Headroom Considerations
    4. 7.4 Output DC Error and Drift Calculations and the Effect of Resistor Imbalances
    5. 7.5 Noise Analysis
    6. 7.6 Factors Influencing Harmonic Distortion
    7. 7.7 Driving Capacitive Loads
    8. 7.8 Thermal Analysis
  9. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 Terminology and Application Assumptions
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Differential I/O
      2. 8.3.2 Power-Down Control Pin (PD)
        1. 8.3.2.1 Operating the Power Shutdown Feature
      3. 8.3.3 Input Overdrive Operation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation from Single-Ended Sources to Differential Outputs
        1. 8.4.1.1 AC-Coupled Signal Path Considerations for Single-Ended Input to Differential Output Conversion
        2. 8.4.1.2 DC-Coupled Input Signal Path Considerations for Single-Ended to Differential Conversion
        3. 8.4.1.3 Resistor Design Equations for the Single-Ended to Differential Configuration of the FDA
        4. 8.4.1.4 Input Impedance for the Single-Ended to Differential FDA Configuration
      2. 8.4.2 Differential-Input to Differential-Output Operation
        1. 8.4.2.1 AC-Coupled, Differential-Input to Differential-Output Design Issues
        2. 8.4.2.2 DC-Coupled, Differential-Input to Differential-Output Design Issues
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Designing Attenuators
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Interfacing to High-Performance ADCs
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
        1. 10.1.1.1 TINA Simulation Model Features
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RUN|10
  • RGT|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.8 Typical Characteristics: 3-V Single Supply

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Rf = 402 Ω, Vout = 100 mVPP, see Figure 7-1 and Table 8-1 for resistor values
Figure 6-19 Small-Signal Frequency Response vs Gain
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Vout = 100 mVPP, see Figure 7-1 with Vocm adjusted
Figure 6-21 Small-Signal Frequency response vs Vocm
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100 mVPP at load, Av = 2 (see Figure 7-11), two series Ro added at output before Cload
Figure 6-23 Small-Signal Frequency Response vs Cload
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50-MHz input, 0.3-ns input edge rate, single-ended input to differential output, DC coupled, see Figure 7-3
Figure 6-25 Small- and Large-Signal Step Response
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G = 5 V/V, 50-MHz input, 0.3-ns input edge rate, single-ended input to differential output, see Figure 7-1
Figure 6-27 Small- and Large-Signal Step Response
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Simulated with 2-ns input transition time,
(see Figure 7-3)
Figure 6-29 Small- and Large-Signal Step Settling Time
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2-VPP output, see Figure 7-1 with Vs+ = 3 V, Vocm = 1.5 V
Figure 6-31 Harmonic Distortion Over Frequency
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1 VPP each tone, see Figure 7-1 with Vs+ = 3 V, Vocm = 1.5 V
Figure 6-33 IMD2 and IM3 Over Frequency
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f = 10 MHz, 2-VPP output,
see Figure 7-3 with Vocm adjusted
Figure 6-35 Harmonic Distortion vs Vocm
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See Figure 7-1 with VCC = 3 V and Vocm = 1.5 V
 
Figure 6-20 Frequency Response vs Vopp
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Vout = 100 mVPP, see Figure 7-1 with the Rload adjusted
Figure 6-22 Small-Signal Frequency Response vs Rload
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Two Ro at output to differential Cload in parallel with 500 Ω, see Figure 7-11 and Table 8-1
Figure 6-24 Recommended Ro vs Cload
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500-mVPP output into 22-pF Cload, see Figure 7-11 with Vs+ = 3 V and Vocm = 1.5 V
Figure 6-26 Step Response into Capacitive Load
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G = 5 V/V, 500-mVpp output into 22-pF Cload, see Figure 7-11 and Table 8-1
Figure 6-28 Step Response into Capacitive Load
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Single-ended to differential gain of 2
(see Figure 7-3), > 2 × input overdrive
Figure 6-30 Overdrive Recovery Performance
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f = 10 MHz, see Figure 7-1 with Vs+ = 3 V, Vocm = 1.5 V
Figure 6-32 Harmonic Distortion vs Output Swing
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f = 10 MHz, see Figure 7-1 with Vs+ = 3 V, Vocm = 1.5 V
Figure 6-34 Harmonic Distortion vs Rload
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f = 10 MHz, 2-VPP output,
see Figure 7-1 and Table 8-1 for gain setting
Figure 6-36 Harmonic Distortion vs Gain