SBOS778D April   2016  – April 2021 THS4551

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Companion Devices
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: (VS+) – (VS–) = 5 V
    6. 7.6 Electrical Characteristics: (VS+) – (VS–) = 3 V
    7. 7.7 Typical Characteristics: (VS+) – (VS–) = 5 V
    8. 7.8 Typical Characteristics: (VS+) – (VS–) = 3 V
    9. 7.9 Typical Characteristics: 3-V to 5-V Supply Range
  8. 8 Parameter Measurement Information
    1. 8.1 Example Characterization Circuits
    2. 8.2 Output Interface Circuit for DC-Coupled Differential Testing
    3. 8.3 Output Common-Mode Measurements
    4. 8.4 Differential Amplifier Noise Measurements
    5. 8.5 Balanced Split-Supply Versus Single-Supply Characterization
    6. 8.6 Simulated Characterization Curves
    7. 8.7 Terminology and Application Assumptions
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Differential Open-Loop Gain and Output Impedance
      2. 9.3.2 Setting Resistor Values Versus Gain
      3. 9.3.3 I/O Headroom Considerations
      4. 9.3.4 Output DC Error and Drift Calculations and the Effect of Resistor Imbalances
    4. 9.4 Device Functional Modes
      1. 9.4.1 Operation from Single-Ended Sources to Differential Outputs
        1. 9.4.1.1 AC-Coupled Signal Path Considerations for Single-Ended Input to Differential Output Conversions
        2. 9.4.1.2 DC-Coupled Input Signal Path Considerations for Single-Ended to Differential Conversions
      2. 9.4.2 Operation from a Differential Input to a Differential Output
        1. 9.4.2.1 AC-Coupled, Differential-Input to Differential-Output Design Issues
        2. 9.4.2.2 DC-Coupled, Differential-Input to Differential-Output Design Issues
      3. 9.4.3 Input Overdrive Performance
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Noise Analysis
      2. 10.1.2 Factors Influencing Harmonic Distortion
      3. 10.1.3 Driving Capacitive Loads
      4. 10.1.4 Interfacing to High-Performance Precision ADCs
      5. 10.1.5 Operating the Power Shutdown Feature
      6. 10.1.6 Designing Attenuators
      7. 10.1.7 The Effect of Adding a Feedback Capacitor
    2. 10.2 Typical Applications
      1. 10.2.1 An MFB Filter Driving an ADC Application
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curves
      2. 10.2.2 Differential Transimpedance Output to a High-Grade Audio PCM DAC Application
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curves
      3. 10.2.3 ADC3k Driver with a 2nd-Order RLC Interstage Filter Application
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
        3. 10.2.3.3 Application Curve
  11. 11Power Supply Recommendations
    1. 11.1 Thermal Analysis
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Board Layout Recommendations
    2. 12.2 Layout Example
    3. 12.3 EVM Board
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 TINA-TI Simulation Model Features
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.3.2 Setting Resistor Values Versus Gain

The THS4551 offers considerable flexibility in the configuration and selection of resistor values. The design starts with the selection of the feedback resistor value. The 1-kΩ feedback resistor value used for the characterization curves is a good compromise between power, noise, and phase margin considerations. With the feedback resistor values selected (and set equal on each side) the input resistors are set to obtain the desired gain with input impedance also set with these input resistors. Differential I/O designs provide an input impedance that is the sum of the two input resistors. Single-ended input to differential output designs present a more complicated input impedance. Most characteristic curves implement the single-ended to differential design as the more challenging requirement over differential-to-differential I/O.

For single-ended, matched, input impedance designs, Table 9-1 illustrates the suggested standard resistors set to approximately a 1-kΩ feedback. This table assumes a 50-Ω source and a 50-Ω input match and uses a single resistor on the non-signal input side for gain matching. Better matching is possible using the same three resistors on the non-signal input side as on the input side. Figure 9-4 shows the element values and naming convention for the gain of 1-V/V configuration where the gain is defined from the matched input at RT to the differential output.

GUID-48AC86E9-F3D1-4782-BD45-6F351F4F5C6B-low.gifFigure 9-4 Single-Ended to Differential Gain of 1 V/V with Input Matching Using Standard Resistor Values

Starting from a target feedback resistor value, the desired input matching impedance, and the target gain (AV), the required input RT value is given by solving the quadratic of Equation 1.

Equation 1. GUID-ED801982-7E7F-4A4D-8B55-F7261366456D-low.gif

When this value is derived, the required input side gain resistor is given by Equation 2 and then the single value for RG2 on the non-signal input side is given by Equation 3:

Equation 2. GUID-7CCECD0D-E4C2-4FB1-9732-EB9C85D7D940-low.gif
Equation 3. GUID-79A952F6-37EF-4088-8CFD-F05F9A75714E-low.gif

Using these expressions to generate a swept gain table of values results in Table 9-1, where the best standard 1% resistor values are shown to minimize input impedance and gain error to target.

Table 9-1 Swept Gain 50-Ω Input Match with RF = 1-kΩ (±1 Standard Values)
GAIN (V/V)RFRG1RTRG2ZINAV
0.110001000049.91000049.660.09965
1100097651.1100049.21.0096
2102049952.352348.91.988
510001875921550.25.057
10102088.769.811850.610.09

Where an input impedance match is not required, simply set the input resistor to obtain the desired gain without an additional resistor to ground (remove RT in Figure 9-4). This scenario is common when coming from the output of another single-ended op amp (such as the OPA192). This single-ended to differential stage shows a higher input impedance than the physical RG as given by the expression for ZA (active input impedance) shown as Equation 4.

Equation 4. GUID-B46D7893-DD78-4EB1-BB5A-CE8879006DC2-low.gif

Using Equation 4 for the gain of 1 V/V with all resistors equal to 1-kΩ shows an input impedance of 1.33 kΩ. The increased input impedance comes from the common-mode input voltage at the amplifier pins moving in the same direction as the input signal. The common-mode input voltage must move to create the current in the non-signal input RG resistor to produce the inverted output. The current flow into the signal-side input resistor is impeded because the common-mode input voltage moves with the input signal, thus increasing the apparent input impedance in the signal input path.