SBOS778D April   2016  – April 2021 THS4551

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Companion Devices
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: (VS+) – (VS–) = 5 V
    6. 7.6 Electrical Characteristics: (VS+) – (VS–) = 3 V
    7. 7.7 Typical Characteristics: (VS+) – (VS–) = 5 V
    8. 7.8 Typical Characteristics: (VS+) – (VS–) = 3 V
    9. 7.9 Typical Characteristics: 3-V to 5-V Supply Range
  8. 8 Parameter Measurement Information
    1. 8.1 Example Characterization Circuits
    2. 8.2 Output Interface Circuit for DC-Coupled Differential Testing
    3. 8.3 Output Common-Mode Measurements
    4. 8.4 Differential Amplifier Noise Measurements
    5. 8.5 Balanced Split-Supply Versus Single-Supply Characterization
    6. 8.6 Simulated Characterization Curves
    7. 8.7 Terminology and Application Assumptions
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Differential Open-Loop Gain and Output Impedance
      2. 9.3.2 Setting Resistor Values Versus Gain
      3. 9.3.3 I/O Headroom Considerations
      4. 9.3.4 Output DC Error and Drift Calculations and the Effect of Resistor Imbalances
    4. 9.4 Device Functional Modes
      1. 9.4.1 Operation from Single-Ended Sources to Differential Outputs
        1. 9.4.1.1 AC-Coupled Signal Path Considerations for Single-Ended Input to Differential Output Conversions
        2. 9.4.1.2 DC-Coupled Input Signal Path Considerations for Single-Ended to Differential Conversions
      2. 9.4.2 Operation from a Differential Input to a Differential Output
        1. 9.4.2.1 AC-Coupled, Differential-Input to Differential-Output Design Issues
        2. 9.4.2.2 DC-Coupled, Differential-Input to Differential-Output Design Issues
      3. 9.4.3 Input Overdrive Performance
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Noise Analysis
      2. 10.1.2 Factors Influencing Harmonic Distortion
      3. 10.1.3 Driving Capacitive Loads
      4. 10.1.4 Interfacing to High-Performance Precision ADCs
      5. 10.1.5 Operating the Power Shutdown Feature
      6. 10.1.6 Designing Attenuators
      7. 10.1.7 The Effect of Adding a Feedback Capacitor
    2. 10.2 Typical Applications
      1. 10.2.1 An MFB Filter Driving an ADC Application
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curves
      2. 10.2.2 Differential Transimpedance Output to a High-Grade Audio PCM DAC Application
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curves
      3. 10.2.3 ADC3k Driver with a 2nd-Order RLC Interstage Filter Application
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
        3. 10.2.3.3 Application Curve
  11. 11Power Supply Recommendations
    1. 11.1 Thermal Analysis
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Board Layout Recommendations
    2. 12.2 Layout Example
    3. 12.3 EVM Board
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 TINA-TI Simulation Model Features
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.9 Typical Characteristics: 3-V to 5-V Supply Range

at TA ≈ 25°C, VOCM pin = open, RF = 1 kΩ, RL = 1 kΩ, VOUT = 2 VPP, 50-Ω input match, G = 1 V/V, PD = VS+, single-ended input, differential output, and input and output referenced to default midsupply for ac-coupled tests (unless otherwise noted); see Figure 8-1 for a gain of 1-V/V test circuit

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Simulated with a 1-kΩ differential load and 0.6-pF internal feedback capacitors removed
Figure 7-37 Main Amplifier Differential Open-Loop Gain and Phase vs Frequency
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Figure 7-39 Input Spot Noise vs Frequency
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Common-mode input to differential output, simulated with G = 1 V/V
Figure 7-41 CMRR vs Frequency
GUID-D5422E04-E46F-4F1C-B980-35E2971E25A7-low.gifFigure 7-43 Common-Mode Voltage, Small- and Large-Signal Response (VOCM Pin Driven)
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The VOCM pin is either driven to midsupply by low-impedance source or allowed to float and default to midsupply
Figure 7-45 Output Common-Mode Noise vs Frequency
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Simulated with single-ended to differential gain of 1 , PSRR for negative supply to differential output
Figure 7-47 –PSRR vs VOCM Approaching VS–
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Total of 234 DGK units trimmed at a 5-V supply
Figure 7-49 Input Offset Voltage (VIO)
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5-V and 3-V delta from 25°C VIO, 50 DGK units
Figure 7-51 Input Offset Voltage vs Temperature
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–40°C to +125°C endpoint drift, total of 62 DGK units
Figure 7-53 Input Offset Voltage Drift Histogram
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Maximum differential output swing, VOCM at midsupply
Figure 7-55 ±Maximum VOUT vs Differential Load Resistance
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VOCM input floating, total of 240 units
Figure 7-57 Common-Mode Output Offset from VS+ / 2 Default Value Histogram
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5 MHz, 2-VPP input, G = 1 V/V, see Figure 8-1
Figure 7-59 PD Turn-On Waveform
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Simulated closed-loop differential output impedance
Figure 7-38 Closed-Loop Output Impedance vs Frequency
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Differential mode output to common-mode output, simulated with G = 1 V/V
Figure 7-40 Output Balance vs Frequency
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Single-ended to differential gain of 1, PSRR simulated to differential output
Figure 7-42 Power-Supply Rejection Ratio vs Frequency
GUID-950069AE-2977-466E-B201-24D4A43F544B-low.gifFigure 7-44 Common-Mode Voltage, Small- and Large-Step Response (VOCM Pin Driven)
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Average VOCM output offset of 39 units, standard deviation < 2 mV
Figure 7-46 VOCM Offset vs VOCM Setting
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Simulated with single-ended to differential gain of 1, PSRR for positive supply to differential output
Figure 7-48 +PSRR vs VOCM Approaching VS+
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Total of 234 DGK units trimmed at a 5-V supply
Figure 7-50 Input Offset Current (IOS)
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5-V and 3-V delta from 25°C IOS, 50 DGK units
Figure 7-52 Input Offset Current vs Temperature
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–40°C to +125°C endpoint drift, total of 62 DGK units
Figure 7-54 Input Offset Current Drift Histogram
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Figure 7-56 Supply Current vs PD Voltage
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VOCM Input driven to midsupply, total of 240 units
Figure 7-58 Common-Mode Output Offset from Driven VOCM Histogram
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5 MHz, 2-VPP input, G = 1 V/V, see Figure 8-1
Figure 7-60 PD Turn-Off Waveform