SBOS831B December   2016  – June 2021 THS4552

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: (VS+) – (VS–) = 5 V
    6. 6.6 Electrical Characteristics: (VS+) – (VS–) = 3 V
    7. 6.7 Typical Characteristics: (VS+) – (VS–) = 5 V
    8. 6.8 Typical Characteristics: (VS+) – (VS–) = 3 V
    9. 6.9 Typical Characteristics: 3 V to 5 V Supply Range
  7. Parameter Measurement Information
    1. 7.1 Example Characterization Circuits
    2. 7.2 Output Interface Circuit for DC-Coupled Differential Testing
    3. 7.3 Output Common-Mode Measurements
    4. 7.4 Differential Amplifier Noise Measurements
    5. 7.5 Balanced Split-Supply Versus Single-Supply Characterization
    6. 7.6 Simulated Characterization Curves
    7. 7.7 Terminology and Application Assumptions
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Differential Open-Loop Gain and Output Impedance
      2. 8.3.2 Setting Resistor Values Versus Gain
      3. 8.3.3 I/O Headroom Considerations
      4. 8.3.4 Output DC Error and Drift Calculations and the Effect of Resistor Imbalances
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation from Single-Ended Sources to Differential Outputs
        1. 8.4.1.1 AC-Coupled Signal Path Considerations for Single-Ended Input to Differential Output Conversions
        2. 8.4.1.2 DC-Coupled Input Signal Path Considerations for Single-Ended to Differential Conversions
      2. 8.4.2 Operation from a Differential Input to a Differential Output
        1. 8.4.2.1 AC-Coupled, Differential-Input to Differential-Output Design Issues
        2. 8.4.2.2 DC-Coupled, Differential-Input to Differential-Output Design Issues
      3. 8.4.3 Input Overdrive Performance
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Noise Analysis
      2. 9.1.2 Factors Influencing Harmonic Distortion
      3. 9.1.3 Driving Capacitive Loads
      4. 9.1.4 Interfacing to High-Performance Precision ADCs
      5. 9.1.5 Operating the Power Shutdown Feature
      6. 9.1.6 Channel-to-Channel Crosstalk
      7. 9.1.7 Channel-to-Channel Mismatch
      8. 9.1.8 Designing Attenuators
      9. 9.1.9 The Effect of Adding a Feedback Capacitor
    2. 9.2 Typical Applications
      1. 9.2.1 An MFB Filter Driving an ADC Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Differential Transimpedance Output to a High-Grade Audio PCM DAC Application
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
      3. 9.2.3 ADC3k Driver with a 2nd-Order RLC Interstage Filter Application
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 Thermal Analysis
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Board Layout Recommendations
    2. 11.2 Layout Example
    3. 11.3 EVM Board
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 TINA-TI Simulation Model Features
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Typical Characteristics: (VS+) – (VS–) = 5 V

at TA ≈ 25°C, VOCM pin = open, RF = 1 kΩ, RL = 1 kΩ, VOUT = 2 VPP, 50 Ω input match, G = 1 V/V, PD = VS+, single-ended input, differential output, and input and output referenced to default midsupply for ac-coupled tests (unless otherwise noted); see Figure 7-1 for a gain of 1 V/V test circuit

GUID-8ACA0A11-1AF8-4906-81CB-E26CDCC22040-low.gif
VOUT = 20 mVPP, see Figure 7-1 and Table 8-1 for resistor values
Figure 6-1 Small-Signal Frequency Response vs Gain
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VOUT = 20 mVPP , see Figure 7-1 with VOCM adjusted
Figure 6-3 Small-Signal Frequency Response vs VOCM
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VOUT = 20 mVPP at load, G = 1, two series RO added at output before capacitive load (CL)
Figure 6-5 Small-Signal Frequency Response vs CL
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G = 1 V/V, 5 MHz input, single-ended to differential output
Figure 6-7 Small- and Large-Signal Step Response
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G = 2 V/V, 5 MHz input, single-ended input to differential output
Figure 6-9 Small- and Large-Signal Step Response
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Simulated with G = 1 V/V
Figure 6-11 Small- and Large-Signal Step Settling Time
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G = 1 V/V, VOUT = 2 VPP
Figure 6-13 Harmonic Distortion vs Frequency
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G = 1 V/V, VOUT = 1 VPP each tone
Figure 6-15 Intermodulation Distortion (IMD2 and IMD3) vs Frequency
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G = 1 V/V, VOUT = 2 VPP, with VOCM adjusted
Figure 6-17 Harmonic Distortion vs VOCM
GUID-97E10E34-7C46-4F7C-8B0B-B50B487FBAAB-low.gifFigure 6-2 Frequency Response vs VOUT
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VOUT = 20 mVPP, see Figure 7-1 with load resistance (RL) adjusted
Figure 6-4 Small-Signal Frequency Response vs RL
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Output resistance (RO) is two series output resistors to a differential CL in parallel with a 1 kΩ load resistance
Figure 6-6 Recommended RO vs CL
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G = 1 V/V, VOUT = 500 mV step into 22 pF CL, see Figure 7-4
Figure 6-8 Step Response Into Capacitive Load
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G = 2 V/V, VOUT = 500 mV step into 22 pF CL, see Figure 7-4
Figure 6-10 Step Response Into Capacitive Load
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Single-ended to differential gain of 2, 2X input overdrive
Figure 6-12 Overdrive Recovery Performance
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G = 1 V/V
Figure 6-14 Harmonic Distortion vs Output Swing
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G = 1 V/V, VOUT = 2 VPP, with RL adjusted
Figure 6-16 Harmonic Distortion vs RL
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VOUT = 2 VPP, see Table 8-1 for gain setting
Figure 6-18 Harmonic Distortion vs Gain