SBOS831B December   2016  – June 2021 THS4552

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: (VS+) – (VS–) = 5 V
    6. 6.6 Electrical Characteristics: (VS+) – (VS–) = 3 V
    7. 6.7 Typical Characteristics: (VS+) – (VS–) = 5 V
    8. 6.8 Typical Characteristics: (VS+) – (VS–) = 3 V
    9. 6.9 Typical Characteristics: 3 V to 5 V Supply Range
  7. 7 Parameter Measurement Information
    1. 7.1 Example Characterization Circuits
    2. 7.2 Output Interface Circuit for DC-Coupled Differential Testing
    3. 7.3 Output Common-Mode Measurements
    4. 7.4 Differential Amplifier Noise Measurements
    5. 7.5 Balanced Split-Supply Versus Single-Supply Characterization
    6. 7.6 Simulated Characterization Curves
    7. 7.7 Terminology and Application Assumptions
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Differential Open-Loop Gain and Output Impedance
      2. 8.3.2 Setting Resistor Values Versus Gain
      3. 8.3.3 I/O Headroom Considerations
      4. 8.3.4 Output DC Error and Drift Calculations and the Effect of Resistor Imbalances
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation from Single-Ended Sources to Differential Outputs
        1. 8.4.1.1 AC-Coupled Signal Path Considerations for Single-Ended Input to Differential Output Conversions
        2. 8.4.1.2 DC-Coupled Input Signal Path Considerations for Single-Ended to Differential Conversions
      2. 8.4.2 Operation from a Differential Input to a Differential Output
        1. 8.4.2.1 AC-Coupled, Differential-Input to Differential-Output Design Issues
        2. 8.4.2.2 DC-Coupled, Differential-Input to Differential-Output Design Issues
      3. 8.4.3 Input Overdrive Performance
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Noise Analysis
      2. 9.1.2 Factors Influencing Harmonic Distortion
      3. 9.1.3 Driving Capacitive Loads
      4. 9.1.4 Interfacing to High-Performance Precision ADCs
      5. 9.1.5 Operating the Power Shutdown Feature
      6. 9.1.6 Channel-to-Channel Crosstalk
      7. 9.1.7 Channel-to-Channel Mismatch
      8. 9.1.8 Designing Attenuators
      9. 9.1.9 The Effect of Adding a Feedback Capacitor
    2. 9.2 Typical Applications
      1. 9.2.1 An MFB Filter Driving an ADC Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Differential Transimpedance Output to a High-Grade Audio PCM DAC Application
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
      3. 9.2.3 ADC3k Driver with a 2nd-Order RLC Interstage Filter Application
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 Thermal Analysis
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Board Layout Recommendations
    2. 11.2 Layout Example
    3. 11.3 EVM Board
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 TINA-TI Simulation Model Features
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics: (VS+) – (VS–) = 5 V

at TA ≈ 25°C, VOCM pin = open, RF = 1 kΩ, RL = 1 kΩ, VOUT = 2 VPP, 50 Ω input match, G = 1 V/V, PD = VS+, single-ended input, differential output, and input and output referenced to default midsupply for ac-coupled tests (unless otherwise noted); specifications are per channel; see Figure 7-1 for a gain of 1-V/V test circuit
PARAMETERTEST CONDITIONSMINTYPMAXUNITTEST
LEVEL(1)
AC PERFORMANCE
SSBWSmall-signal bandwidthVOUT = 20 mVPP, G = 1, peaking (< 1.0 dB)150MHzC
VOUT = 20 mVPP, G = 275C
VOUT = 20 mVPP, G = 1015C
GBPGain-bandwidth productVOUT = 20 mVPP, G = 100135MHzC
LSBWLarge-signal bandwidthVOUT = 2 VPP, G = 137MHzC
Bandwidth for 0.1-dB flatnessVOUT = 2 VPP, G = 115MHzC
SRSlew rate(2)VOUT = 4 VPP, full-power bandwidth (FPBW),
RL = 1 kΩ		220V/µsC
tR, tFRise and fall timeVOUT = 0.5 V step, G = 1, input tR = 2 ns6nsC
tSETTLESettling timeTo 0.1%, VOUT = 0.5 V step, input tR = 2 ns, G = 130nsC
To 0.01%,VOUT = 0.5 V step, input tR = 2 ns, G = 150C
Overshoot and undershootVOUT = 0.5 V step G = 1, input tR = 2 ns8%C
HD2Second-order harmonic distortionf = 100 kHz, VOUT = 2 VPP, G = 1, RL = 1 kΩ–128dBcC
f = 100 kHz, VOUT = 8 VPP, G = 1, RL = 1 kΩ–124C
HD3Third-order harmonic distortionf = 100 kHz, VOUT = 2 VPP, G = 1, RL = 1 kΩ–139dBcC
f = 100 kHz, VOUT = 8 VPP, G = 1, RL = 1 kΩ–131C
Input voltage noisef > 500 Hz, 1/f < 150 Hz3.3nV/√ HzC
Input current noisef > 20 kHz, 1/f <10 kHz0.5pA/√ HzC
Overdrive recovery timeG = 2, 2X output overdrive, dc coupled50nsC
Closed-loop output impedancef = 100 kHz (differential), G = 10.02ΩC
Channel-to-channel crosstalk2 VPP output on one channel, 1 MHz–80dBcC
DC PERFORMANCE(5)
AOLOpen-loop voltage gain±3 V differential-to-differential, 1 kΩ load105125dBA
VIOInput-referred offset voltageTA = 25°C–175±50175µVA
TA = 0°C to +70°C–225265B
TA = –40°C to +85°C–295295B
TA = –40°C to +125°C–295375B
Input offset voltage drift(3)TA = –40°C to +125°C (PW package)–2.0±0.452.0µV/°CB
Channel-to-channel input offset voltage mismatchTA = 25°C (PW package)–250250µVA
Input offset voltage drift mismatchTA = –40°C to +125°C (PW package)–2.72.7µV/°CB
IIBInput bias current
(positive current out-of-node)		TA = 25°C1.01.5µAA
TA = 0°C to +70°C1.73B
TA = –40°C to +85°C1.80B
TA = –40°C to +125°C2.0B
Input bias current drift(3)TA = –40°C to +125°C23.35.0nA/°CB
DC PERFORMANCE (continued)
IOSInput offset currentTA = 25°C–50±1050nAA
TA = 0°C to +70°C–5763B
TA = –40°C to +85°C–6867B
TA = –40°C to +125°C–6878B
Input offset current mismatchTA = 25°C–6565nAD
Input offset current drift(3)TA = –40°C to +125°C (PW package)–240±20240pA/°CB
Offset current drift mismatchTA = –40°C to +125°C (PW package)–260±20260pA/°CB
INPUT
Common-mode input, low> 90 dB CMRR at input range limitsTA = 25°C(VS–) – 0.2(VS–) – 0.1VA
TA = –40°C to +125°C(VS–) – 0.1VS–B
Common-mode input, high> 90-dB CMRR at input range limitsTA = 25°C(VS+) – 1.2(VS+) – 1.1VA
TA = –40°C to +125°C(VS+) – 1.3(VS+) – 1.2B
CMRRCommon-mode rejection ratioInput pins at [(VS+) – (VS–)] / 293110dBA
Input impedance differential modeInput pins at [(VS+) – (VS–)] / 2100 || 1.2kΩ || pFC
OUTPUT
Output voltage, lowTA = 25°C(VS–) + 0.2(VS–) + 0.23VA
TA = –40°C to +125°C(VS–) + 0.2(VS–) + 0.22B
Output voltage, highTA = 25°C(VS+) – 0.23(VS+) – 0.2VA
TA = –40°C to +125°C(VS+) – 0.22(VS+) – 0.2B
Continuous output currentTA = 25°C, ±2.5 V, RL= 40 Ω,
VOCM offset < ±20 mV		±60±65mAA
TA = –40°C to +125°C, ±2.1 V, RL= 40 Ω,
VOCM offset < ±20 mV		±50B
Linear output currentTA = 25°C, ±2.1 V, RL= 50 Ω, AOL > 80 dB±40±45mAA
TA = –40°C to +125°C, ±1.6 V, RL= 50 Ω,
AOL > 80 dB		±30B
POWER SUPPLY
Specified operating voltage2.755.4VB
IQQuiescent operating current per channelTA ≈ 25°C(6), VS+ = 5 V1.281.371.44mAA
TA = –40°C to +125°C, VS+ = 5 V0.971.92B
Supply current at maximum operating supply per channelTA = 25°C, VS+ = 5.4 V1.331.361.46mAD
dIQ/dTQuiescent current temperature coefficient per channelVS+ = 5 V2.43.95.4µA/°CB
±PSRRPower-supply rejection ratioEither supply pin to differential VOUT93110dBA
POWER-DOWN
Enable voltage thresholdSpecified on above (VS–) + 1.15 V(VS–) + 1.15VA
Disable voltage thresholdSpecified off below (VS–) + 0.55 V(VS–) + 0.55VA
Disable pin bias currentPD = VS– → VS+–100±10100nAA
Power-down quiescent currentDisable logic at (VS–) + 0.55 V–215µAA
Disable logic at (VS–)–215A
tONTurn-on time delayTime from PD = low to VOUT = 90% of final value700nsC
tOFFTurn-off time delayTime from PD = low to VOUT = 10% of final value100nsC
OUTPUT COMMON-MODE VOLTAGE (VOCM) CONTROL(4) (see Figure 7-5)
SSBWSmall-signal bandwidthVOCM = 100 mVPP at the control pin40MHzC
LSBWLarge-signal bandwidthVOCM = 1 VPP at the control pin8MHzC
SRSlew rate(2)From 1-VPP LSBW18V/µsC
Output common-mode noise
(≥ 2 kHz)		VOCM pin driven from low impedance15nV/√ HzC
GainVOCM control pin input to output average voltage (see Figure 7-5)0.9970.9991.001V/VA
Input bias current–100±10100nAA
DC output balance (differential mode to common-mode output)VOUT = ±1 V85dBC
Output balanceSSBWVOUT = 100 mVPP (output balance drops –3 dB from the 85-dB dc level)300kHzC
LSBWVOUT = 2 VPP (output balance drops –3 dB from the 85-dB dc level)300C
Input impedance
(VOCM pin input)		150 || 7kΩ || pFC
Default voltage offset from
[(VS+) – (VS–)] / 2		VOCM pin open–15±215mVA
Default voltage offset drift from
[(VS+) – (VS–)] / 2		TA = –40°C to +125°C153555µA/°CB
CM VOSCommon-mode offset voltageVOCM pin driven to [(VS+) – (VS–)] / 2TA = 25°C–5.0±15.0mVA
TA = 0°C to +70°C–5.255.5B
TA = –40°C to +85°C–5.75.6B
TA = –40°C to +125°C–5.76.0B
Common-mode offset voltage drift(3)TA = –40°C to +125°C–10±210µV/°CB
Common-mode headroom to negative supply –PSRR test (supply to VOD)–PSRR > 80 dB0.55VD
Common-mode loop supply headroom to negative supply< ±15 mV shift from midsupply CM VOSTA = 25°C0.55VA
TA = 0°C to +70°C0.6B
TA = –40°C to +85°C0.65B
TA = –40°C to +125°C0.7B
Common-mode headroom to positive supply +PSRR test (supply to VOD)+PSRR > 80 dB1.2VD
Common-mode loop supply headroom to positive supply< ±15 mV shift from mid-supply CM VOSTA = 25°C1.2VA
TA = 0°C to 70°C1.25B
TA = –40°C to +85°C1.3B
TA = –40°C to +125°C1.3B
(1) Test levels (all values set by characterization and simulation): (A) 100% tested at TA ≈ 25°C. (B) Not tested in production; limits set by characterization and simulation. (C) Typical value only for information.
(2) This slew rate is the average of the rising and falling time estimated from the sinusoidal large-signal bandwidth as: (VP / √ 2) × 2π × f–3dB.
(3) Input offset voltage drift, input bias current drift, and input offset current drift are the mean ±1-sigma values calculated by taking measurements at the maximum-range ambient temperature end points, computing the difference, and dividing by the temperature range. Maximum drift specifications are set by mean ±4 σ on the device distributions tested over a –40°̊C to +125°̊C ambient temperature range. Drift is not specified by final ATE testing or QA sample test.
(4) Specifications are from the input VOCM pin to the differential output average voltage.
(5) Currents out of pin are treated as a positive polarity (with the exception of the power-supply pins).
(6) TA = 25°C and ICC ≈ 1.37 mA. The test limit is expanded for the ATE ambient range of 22°C to 32°C with a 4 µA/°C ICC temperature coefficient considered; see Figure 10-1.