SBOS431A May   2009  – March 2017 THS6214

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: VS = ±12 V
    6. 6.6  Electrical Characteristics: VS = ±6 V
    7. 6.7  Timing Requirements
    8. 6.8  Typical Characteristics: VS = ±12 V, Full Bias
    9. 6.9  Typical Characteristics: VS = ±12 V, Mid Bias
    10. 6.10 Typical Characteristics: VS = ±12 V, Low Bias
    11. 6.11 Typical Characteristics: VS = ±6 V, Full Bias
    12. 6.12 Typical Characteristics: VS = ±6 V, Mid Bias
    13. 6.13 Typical Characteristics: VS = ±6 V, Low Bias
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Current and Voltage
      2. 7.3.2 Driving Capacitive Loads
      3. 7.3.3 Distortion Performance
      4. 7.3.4 Differential Noise Performance
      5. 7.3.5 DC Accuracy and Offset Control
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Wideband Current-Feedback Operation
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Dual-Supply VDSL Downstream Driver
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Line Driver Headroom Model Requirements
          2. 8.2.2.2.2 Total Driver Power for xDSL Applications
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Board Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage, VS– to VS+ 28 V
Input voltage, VI ±VS V
Differential input voltage, VID ±2 V
Output current, IO Static dc(2) ±500 mA
Continuous power dissipation See Thermal Information
Maximum junction temperature, TJ Under any condition(3) 150 °C
Continuous operation, long-term reliability(4), RHF package only 130
Continuous operation, long-term reliability(4), PWP package only 140
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The THS6214 incorporates a PowerPAD on the underside of the chip. This pad functions as a heatsink and must be connected to a thermally dissipating plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature, which can permanently damage the device. See PowerPAD™ Thermally Enhanced Package (SLMA002) for more information about using the PowerPAD thermally-enhanced package. Under high-frequency ac operation (greater than 10 kHz), the short-term output current capability is much greater than the continuous dc output current rating. This short-term output current rating is approximately 8.5 times the dc capability, or approximately ±850 mA.
(3) The absolute maximum junction temperature under any condition is limited by the constraints of the silicon process.
(4) The absolute maximum junction temperature for continuous operation is limited by the package constraints. Operation above this temperature may result in reduced reliability and/or lifetime of the device.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
Machine model (MM) ±100
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VS Supply voltage, VS– to VS+ 10 28 V
TJ Operating junction temperature 130 °C
TA Ambient operating air temperature 25 85 °C

6.4 Thermal Information

THERMAL METRIC(1) THS6214 UNIT
RHF (VQFN) PWP (HTSSOP)
24 PINS 24 PINS
RθJA Junction-to-ambient thermal resistance 33.2 35.7 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 31.7 22.9 °C/W
RθJB Junction-to-board thermal resistance 11.3 10.1 °C/W
ψJT Junction-to-top characterization parameter 0.4 0.4 °C/W
ψJB Junction-to-board characterization parameter 11.3 10.3 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 3.9 1.7 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics: VS = ±12 V

at TA = 25°C, GDIFF = 10 V/V with RL = 100-Ω differential load, RADJ = 0 Ω, active impedance circuit configuration, and full bias (unless otherwise noted); each port is independently tested
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEST LEVEL(1)
AC PERFORMANCE
Small-signal bandwidth, –3 dB GDIFF = 5 V/V , RF = 1.5 kΩ, VO = 2 VPP 160 MHz C
GDIFF = 10 V/V , RF = 1.5 kΩ, VO = 2 VPP 120 150 B
Over –40°C to +85°C temperature range 100
0.1-dB bandwidth flatness GDIFF = 10 V/V , RF = 1.24 kΩ 114 MHz C
Large-signal bandwidth GDIFF = 10 V/V , RF = 1.24 kΩ, VO = 20 VPP 120 MHz C
Slew rate (10% to 90% level) GDIFF = 10 V/V, VO = 20-V step, differential 3200 3800 V/µs B
TA = –40°C to +85°C 3000 B
Rise and fall time GDIFF = 10 V/V, VO = 2 VPP 5 ns C
2nd-order harmonic distortion GDIFF = 10 V/V,
VO = 2 VPP,
RL = 100-Ω differential		 Full bias, f = 1 MHz –100 –95 dBc B
TA = –40°C to +85°C –90 B
Low bias, f = 1 MHz –96 C
Full bias, f = 10 MHz –75 –70 B
TA = –40°C to +85°C –65 B
Low bias, f = 10 MHz –72 C
3rd-order harmonic distortion GDIFF = 10 V/V,
VO = 2 VPP,
RL = 100-Ω differential		 Full bias, f = 1 MHz –89 –85 dBc B
TA = –40°C to +85°C –80 B
Low bias, f = 1 MHz –85 C
Full bias, f = 10 MHz –73 –65 B
TA = –40°C to +85°C –53 B
Low bias, f = 10 MHz –58 C
Differential input voltage noise f = 1 MHz, input-referred 2.7 3.2 nV/√Hz B
TA = –40°C to +85°C 3.5 B
Differential noninverting current noise f = 1 MHz 1.2 1.4 pA/√Hz B
TA = –40°C to +85°C 1.6 B
Differential inverting current noise f = 1 MHz 17 20 pA/√Hz B
TA = –40°C to +85°C 24 B
DC PERFORMANCE
Open-loop transimpedance gain RL = 100 Ω 330(4) 700 kΩ A
300 B
Input offset voltage ±15 ±50(4) mV A
TA = –40°C to +85°C ±60 B
Input offset voltage drift TA = –40°C to +85°C ±155 µV/°C B
Input offset voltage matching ±0.5 ±5(4) mV A
TA = –40°C to +85°C ±7 B
Noninverting input bias current ±1 ±3.5(4) µA A
TA = –40°C to +85°C ±5.5 B
Noninverting input bias current drift TA = –40°C to +85°C ±30(4) nA/°C B
Inverting input bias current ±8 ±45(4) µA A
TA = –40°C to +85°C ±55 B
Inverting input bias current drift TA = –40°C to +85°C ±154 nA/°C B
Inverting input bias current matching ±8 ±30(4) µA A
TA = –40°C to +85°C ±40 B
INPUT CHARACTERISTICS
Common-mode input range Each input ±9(4) ±9.5 V A
TA = –40°C to +85°C ±8.6 B
Common-mode rejection ratio Each input 53(4) 65 dB A
TA = –40°C to +85°C 49 B
Noninverting input resistance 500 || 2 kΩ || pF C
Inverting input resistance 50 Ω C
OUTPUT CHARACTERISTICS(2)
Output voltage swing RL = 100 Ω, each output ±10.9 V C
RL = 50 Ω, each output ±10.6(4) ±10.8 A
TA = –40°C to +85°C ±10.4 B
RL = 25 Ω, each output ±10.2(4) ±10.4 A
TA = –40°C to +85°C ±10 B
Output current
(sourcing and sinking)		 RL = 25 Ω, based on VO tests ±408(4) ±416 mA A
TA = –40°C to +85°C ±400 B
Short-circuit output current 1 A C
Output impedance f = 1 MHz, differential 0.2 Ω C
Crosstalk f = 1 MHz, VO = 2 VPP, port 1 to port 2 –90 dB C
POWER SUPPLY
Operating voltage ±5(4) ±12 ±14(4) V A
TA = –40°C to +85°C ±5 ±14 C
IS+ quiescent current Per port, full bias (BIAS-1 = 0, BIAS-2 = 0) 19.5(4) 21 22.5(4) mA A
TA = –40°C to +85°C 17 24 B
Per port, mid bias (BIAS-1 = 1, BIAS-2 = 0) 15(4) 16.2 17.4(4) A
TA = –40°C to +85°C 12.8 18.6 B
Per port, low bias (BIAS-1 = 0, BIAS-2 = 1) 10(4) 11.2 12.4(4) A
TA = –40°C to +85°C 8.1 13.2 B
Per port, bias off (BIAS-1 = 1, BIAS-2 = 1) 0.4 0.8(4) A
TA = –40°C to +85°C 1 B
IS– quiescent current Per port, full bias (BIAS-1 = 0, BIAS-2 = 0) 18.5(4) 20 21.5(4) mA A
TA = –40°C to +85°C 16 23 B
Per port, mid bias (BIAS-1 = 1, BIAS-2 = 0) 14(4) 15.2 16.4(4) A
TA = –40°C to +85°C 11.8 17.6 B
Per port, low bias (BIAS-1 = 0, BIAS-2 = 1) 9(4) 10.2 11.6(4) A
TA = –40°C to +85°C 7.1 11.4 B
Per port, bias off (BIAS-1 = 1, BIAS-2 = 1) 0.1 0.3(4) A
TA = –40°C to +85°C 0.8 B
Current through GND pin Per port, full bias (BIAS-1 = 0, BIAS-2 = 0) 1 mA C
+PSRR Positive power-supply rejection ratio Differential 54(4) 66 dB A
TA = –40°C to +85°C 52 B
–PSRR Negative power-supply rejection ratio Differential 52(4) 65 dB A
TA = –40°C to +85°C 50 B
LOGIC
Bias control pin logic threshold Logic 1, with respect to GND(3),
TA = –40°C to +85°C		 1.9 V B
Logic 0, with respect to GND(3),
TA = –40°C to +85°C		 0.8 B
Bias pin quiescent current BIAS-1, BIAS-2 = 0.5 V (logic 0) 20 30(4) µA A
TA = –40°C to +85°C 35 B
BIAS-1, BIAS-2 = 3.3 V (logic 1) 0.3 1(4) A
TA = –40°C to +85°C 1.2 B
Bias pin input impedance 50 kΩ C
Amplifier output impedance Off bias (BIAS-1 = 1, BIAS-2 = 1) 10 || 5 kΩ || pF C

6.6 Electrical Characteristics: VS = ±6 V

at TA = 25°C, GDIFF = 5 V/V with RL = 100-Ω differential load, RADJ = 0 Ω, active impedance circuit configuration, and full bias (unless otherwise noted); each port is independently tested
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEST LEVEL(1)
AC PERFORMANCE
Small-signal bandwidth, –3 dB GDIFF = 5 V/V , RF = 1.5 kΩ, VO = 2 VPP 140 MHz C
GDIFF = 10 V/V , RF = 1.5 kΩ, VO = 2 VPP 110 140 B
Over –40°C to +85°C temperature range 95
0.1-dB bandwidth flatness GDIFF = 10 V/V , RF = 1.24 kΩ 100 MHz C
Large-signal bandwidth GDIFF = 10 V/V , RF = 1.24 kΩ, VO = 20 VPP 120 MHz C
Slew rate (10% to 90% level) GDIFF = 10 V/V, VO = 20-V step, differential 1200 1600 V/µs B
TA = –40°C to +85°C 1000 B
Rise and fall time GDIFF = 10 V/V, VO = 2 VPP 5 ns C
2nd-order harmonic distortion GDIFF = 10 V/V,
VO = 2 VPP,
RL = 100-Ω differential		 Full bias –98 –92 dBc B
TA = –40°C to +85°C –87 B
Low bias –93 C
Full bias –80 –75 B
TA = –40°C to +85°C –68 B
Low bias –74 C
3rd-order harmonic distortion GDIFF = 10 V/V,
VO = 2 VPP,
RL = 100-Ω differential		 Full bias –93 –84 dBc B
TA = –40°C to +85°C –79 B
Low bias –89 C
Full bias –66 –60 B
TA = –40°C to +85°C –54 B
Low bias –55 C
Differential input voltage noise f = 1 MHz, input-referred 2.5 3.0 nV/√Hz B
TA = –40°C to +85°C 3.3 B
Differential noninverting current noise f = 1 MHz 1.2 1.4 pA/√Hz B
TA = –40°C to +85°C 1.6 B
Differential inverting current noise f = 1 MHz 17 20 pA/√Hz B
TA = –40°C to +85°C 24 B
DC PERFORMANCE
Open-loop transimpedance gain RL = 100 Ω 330(4) 650 kΩ A
TA = –40°C to +85°C 300 B
Input offset voltage ±10 ±45(4) mV A
TA = –40°C to +85°C ±55 B
Input offset voltage drift TA = –40°C to +85°C ±155 µV/°C B
Input offset voltage matching Channels 1 to 2 and 3 to 4 only ±0.5 ±5(4) mV A
TA = –40°C to +85°C ±7 B
Noninverting input bias current ±1 ±3.5(4) µA A
TA = –40°C to +85°C ±5.5 B
Noninverting input bias current drift TA = –40°C to +85°C ±30(4) nA/°C B
Inverting input bias current ±8 ±45(4) µA A
TA = –40°C to +85°C ±55 B
Inverting input bias current drift TA = –40°C to +85°C ±135 nA/°C B
Inverting input bias current matching ±8 ±30(4) µA A
TA = –40°C to +85°C ±40 B
INPUT CHARACTERISTICS
Common-mode input range Each input ±2.9(4) ±3.0 V A
TA = –40°C to +85°C ±2.7 B
Common-mode rejection ratio Each input 51(4) 62 dB A
TA = –40°C to +85°C 47 B
Noninverting input resistance 500 || 2 kΩ || pF C
Inverting input resistance 55 Ω C
OUTPUT CHARACTERISTICS(2)
Output voltage swing RL = 100 Ω, each output ±4.9 V C
RL = 50 Ω, each output ±4.75(4) ±4.9 A
TA = –40°C to +85°C ±4.6 B
RL = 25 Ω, each output ±4.55(4) ±4.7 A
TA = –40°C to +85°C ±4.4 B
Output current
(sourcing and sinking)		 RL = 25 Ω, based on VO tests ±182(4) ±188 mA A
TA = –40°C to +85°C ±176 B
Short-circuit output current ±1 A C
Output impedance f = 1 MHz, differential 0.2 Ω C
Crosstalk f = 1 MHz, VO = 2 VPP, port 1 to port 2 –90 dB C
POWER SUPPLY
Operating voltage ±5(4) ±6 ±14(4) V A
TA = –40°C to +85°C ±5 ±14 C
IS+ quiescent current Per port, full bias (BIAS-1 = 0, BIAS-2 = 0) 13(4) 17 21(4) mA A
TA = –40°C to +85°C 10 22 B
Per port, mid bias (BIAS-1 = 1, BIAS-2 = 0) 10.2(4) 13.2 16.2(4) A
TA = –40°C to +85°C 9.3 16.4 B
Per port, low bias (BIAS-1 = 0, BIAS-2 = 1) 7.4(4) 9.4 11.4(4) A
TA = –40°C to +85°C 6.7 11.6 B
Per port, bias off (BIAS-1 = 1, BIAS-2 = 1) 0.5 0.8(4) A
TA = –40°C to +85°C 0.9 B
IS– quiescent current Per port, full bias (BIAS-1 = 0, BIAS-2 = 0) 12(4) 16 20(4) mA A
TA = –40°C to +85°C 9 21 B
Per port, mid bias (BIAS-1 = 1, BIAS-2 = 0) 9.2(4) 12.2 15.2(4) A
TA = –40°C to +85°C 8.3 15.4 B
Per port, low bias (BIAS-1 = 0, BIAS-2 = 1) 6.4(4) 8.4 10.4(4) A
TA = –40°C to +85°C 5.7 10.6 B
Per port, bias off (BIAS-1 = 1, BIAS-2 = 1) 0.1 0.3(4) A
TA = –40°C to +85°C 0.5 B
Current through GND pin Per port, full bias (BIAS-1 = 0, BIAS-2 = 0) 1 mA C
+PSRR Positive power-supply rejection ratio Differential 54(4) 64 dB A
TA = –40°C to +85°C 52 B
–PSRR Negative power-supply rejection ratio Differential 52(4) 63 dB A
TA = –40°C to +85°C 50 B
LOGIC
Bias control pin logic threshold Logic 1, with respect to GND(3),
TA = –40°C to +85°C		 1.9 V B
Logic 0, with respect to GND(3),
TA = –40°C to +85°C		 0.8 B
Bias pin quiescent current BIAS-1, BIAS-2 = 0.5 V (logic 0) 20 30(4) µA A
TA = –40°C to +85°C 35 B
BIAS-1, BIAS-2 = 3.3 V (logic 1) 0.3 1(4) A
TA = –40°C to +85°C 1.2 B
Bias pin input impedance 50 kΩ C
Amplifier output impedance Off bias (BIAS-1 = 1, BIAS-2 = 1) 10 || 5 kΩ || pF C
(1) Test levels: (A) 100% tested at 25°C. Overtemperature limits set by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information.
(2) Test circuit is shown in Figure 1.
(3) The GND pin usable range is from VS– to (VS+ – 5 V).
(4) This specification is 100% tested at 25°C.

6.7 Timing Requirements

MIN NOM MAX UNIT
tON Turn-on time delay: time for IS to reach 50% of final value 1 µs
tOFF Turn-off time delay: time for IS to reach 50% of final value 1 µs

6.8 Typical Characteristics: VS = ±12 V, Full Bias

at TA = 25°C, GDIFF = 10 V/V, GCM = 1 V/V, RADJ = 0 Ω, RF = 1.24 kΩ, and RL = 100 Ω (unless otherwise noted)
THS6214 G001_sbos758.gif
VO = 2 VPP
Figure 1. Small-Signal Frequency Response
THS6214 G003_sbos758.gif
Figure 3. Large-Signal Frequency Response
THS6214 G005_sbos758.gif
Figure 5. Recommended RS vs Capacitive Load
THS6214 G007_sbos758.gif
VO = 2 VPP
Figure 7. Harmonic Distortion vs Frequency
THS6214 G009_sbos758.gif
VO = 2 VPP, f = 1 MHz
Figure 9. Harmonic Distortion vs Supply Voltage
THS6214 G011_sbos758.gif
VO = 2 VPP, f = 1 MHz
Figure 11. Harmonic Distortion vs Noninverting Gain
THS6214 G013_sbos758.gif
Figure 13. Output Voltage and Current Limitations
THS6214 G015_sbos758.gif
Figure 15. Quiescent Current for Full Bias Setting vs RADJ
THS6214 G017_sbos758.gif
Figure 17. Open-Loop Gain and Phase
THS6214 G002_sbos758.gif
VO = 2 VPP
Figure 2. Small-Signal Frequency Response vs Bias Mode
THS6214 G004_sbos758.gif
Figure 4. Pulse Response
THS6214 G006_sbos431.gif
RS optimized for 100% bias
Figure 6. Frequency Response vs Capacitive Load
THS6214 G008_sbos758.gif
f = 1 MHz
Figure 8. Harmonic Distortion vs Output Voltage
THS6214 G010_sbos758.gif
VO = 2 VPP, f = 1 MHz
Figure 10. Harmonic Distortion vs Load Resistance
THS6214 G012_sbos758.gif
Figure 12. Two-Tone, Third-Order Intermodulation Intercept
THS6214 G014_sbos758.gif
Voltage and current noise contributing to differential noise
Figure 14. Input Voltage and Current Noise Density
THS6214 G016_sbos758.gif
Figure 16. PSRR vs Frequency
THS6214 G018_sbos758.gif
Figure 18. Closed-Loop Output Impedance

6.9 Typical Characteristics: VS = ±12 V, Mid Bias

at TA = 25°C, GDIFF = 10 V/V, GCM = 1 V/V, RADJ = 0 Ω, RF = 1.24 kΩ, and RL = 100 Ω (unless otherwise noted)
THS6214 G019_sbos758.gif
VO = 2 VPP
Figure 19. Small-Signal Frequency Response
THS6214 G021_sbos758.gif
Figure 21. Pulse Response
THS6214 G023_sbos758.gif
Figure 23. Recommended RS vs Capacitive Load
THS6214 G025_sbos758.gif
VO = 2 VPP
Figure 25. Harmonic Distortion vs Frequency
THS6214 G027_sbos758.gif
VO = 2 VPP, f = 1 MHz
Figure 27. Harmonic Distortion vs Supply Voltage
THS6214 G029_sbos758.gif
VO = 2 VPP, f = 1 MHz
Figure 29. Harmonic Distortion vs Noninverting Gain
THS6214 G020_sbos758.gif
Figure 20. Large-Signal Frequency Response
THS6214 G022_sbos758.gif
Figure 22. Quiescent Current for Mid Bias Setting vs RADJ
THS6214 G024_sbos431.gif
RS optimized for 100% bias
Figure 24. Frequency Response vs Capacitive Load
THS6214 G026_sbos758.gif
f = 1 MHz
Figure 26. Harmonic Distortion vs Output Voltage
THS6214 G028_sbos758.gif
VO = 2 VPP, f = 1 MHz
Figure 28. Harmonic Distortion vs Load Resistance
THS6214 G030_sbos758.gif
Figure 30. Two-Tone, Third-Order Intermodulation Intercept

6.10 Typical Characteristics: VS = ±12 V, Low Bias

at TA = 25°C, GDIFF = 10 V/V, GCM = 1 V/V, RADJ = 0 Ω, RF = 1.24 kΩ, and RL = 100 Ω (unless otherwise noted)
THS6214 G031_sbos758.gif
VO = 2 VPP
Figure 31. Small-Signal Frequency Response
THS6214 G033_sbos758.gif
Figure 33. Pulse Response
THS6214 G035_sbos758.gif
Figure 35. Recommended RS vs Capacitive Load
THS6214 G037_sbos758.gif
VO = 2 VPP
Figure 37. Harmonic Distortion vs Frequency
THS6214 G039_sbos758.gif
VO = 2 VPP, f = 1 MHz
Figure 39. Harmonic Distortion vs Supply Voltage
THS6214 G041_sbos758.gif
VO = 2 VPP, f = 1 MHz
Figure 41. Harmonic Distortion vs Noninverting Gain
THS6214 G032_sbos758.gif
Figure 32. Large-Signal Frequency Response
THS6214 G034_sbos758.gif
Figure 34. Supply Current for Low Bias Setting vs RADJ
THS6214 G036_sbos431.gif
RS optimized for 100% bias
Figure 36. Frequency Response vs Capacitive Load
THS6214 G038_sbos758.gif
f = 1 MHz
Figure 38. Harmonic Distortion vs Output Voltage
THS6214 G040_sbos758.gif
VO = 2 VPP, f = 1 MHz
Figure 40. Harmonic Distortion vs Load Resistance
THS6214 G042_sbos758.gif
Figure 42. Two-Tone, Third-Order Intermodulation Intercept

6.11 Typical Characteristics: VS = ±6 V, Full Bias

at TA = 25°C, GDIFF = 5 V/V, GCM = 1 V/V, RADJ = 0 Ω, RF = 1.82 kΩ, and RL = 100 Ω (unless otherwise noted)
THS6214 G043_sbos758.gif
VO = 2 VPP
Figure 43. Small-Signal Frequency Response
THS6214 G045_sbos758.gif
Figure 45. Large-Signal Frequency Response
THS6214 G047_sbos758.gif
Figure 47. Recommended RS vs Capacitive Load
THS6214 G049_sbos758.gif
VO = 2 VPP
Figure 49. Harmonic Distortion vs Frequency
THS6214 G051_sbos758.gif
VO = 2 VPP, f = 1 MHz
Figure 51. Harmonic Distortion vs Supply Voltage
THS6214 G053_sbos758.gif
VO = 2 VPP, f = 1 MHz
Figure 53. Harmonic Distortion vs Noninverting Gain
THS6214 G055_sbos758.gif
Figure 55. Quiescent Current for Full Bias Setting vs RADJ
THS6214 G044_sbos758.gif
VO = 2 VPP
Figure 44. Small-Signal Frequency Response vs Bias
THS6214 G046_sbos758.gif
Figure 46. Pulse Response
THS6214 G048_sbos431.gif
RS optimized for 100% bias
Figure 48. Frequency Response vs Capacitive Load
THS6214 G050_sbos758.gif
VO = 2 VPP, f = 1 MHz
Figure 50. Harmonic Distortion vs Output Voltage
THS6214 G052_sbos758.gif
VO = 2 VPP, f = 1 MHz
Figure 52. Harmonic Distortion vs Load Resistance
THS6214 G054_sbos758.gif
Figure 54. Two-Tone, Third-Order Intermodulation Intercept

6.12 Typical Characteristics: VS = ±6 V, Mid Bias

at TA = 25°C, GDIFF = 5 V/V, GCM = 1 V/V, RADJ = 0 Ω, RF = 1.82 kΩ, and RL = 100 Ω (unless otherwise noted)
THS6214 G056_sbos758.gif
VO = 2 VPP
Figure 56. Small-Signal Frequency Response
THS6214 G058_sbos758.gif
Figure 58. Pulse Response
THS6214 G060_sbos758.gif
Figure 60. Recommended RS vs Capacitive Load
THS6214 G062_sbos758.gif
VO = 2 VPP
Figure 62. Harmonic Distortion vs Frequency
THS6214 G064_sbos758.gif
VO = 2 VPP, f = 1 MHz
Figure 64. Harmonic Distortion vs Supply Voltage
THS6214 G066_sbos758.gif
VO = 2 VPP, f = 1 MHz
Figure 66. Harmonic Distortion vs Noninverting Gain
THS6214 G057_sbos758.gif
Figure 57. Large-Signal Frequency Response
THS6214 G059_sbos758.gif
Figure 59. Quiescent Current for Mid Bias Setting vs RADJ
THS6214 G061_sbos431.gif
RS optimized for 100% bias
Figure 61. Frequency Response vs Capacitive Load
THS6214 G063_sbos758.gif
f = 1 MHz
Figure 63. Harmonic Distortion vs Output Voltage
THS6214 G065_sbos758.gif
VO = 2 VPP, f = 1 MHz
Figure 65. Harmonic Distortion vs Load Resistance
THS6214 G067_sbos758.gif
Figure 67. Two-Tone, Third-Order Intermodulation Intercept

6.13 Typical Characteristics: VS = ±6 V, Low Bias

at TA = 25°C, GDIFF = 5 V/V, GCM = 1 V/V, RADJ = 0 Ω, RF = 1.82 kΩ, and RL = 100 Ω (unless otherwise noted)
THS6214 G068_sbos758.gif
VO = 2 VPP
Figure 68. Small-Signal Frequency Response
THS6214 G070_sbos758.gif
Figure 70. Pulse Response
THS6214 G072_sbos758.gif
Figure 72. Recommended RS vs Capacitive Load
THS6214 G074_sbos758.gif
VO = 2 VPP
Figure 74. Harmonic Distortion vs Frequency
THS6214 G076_sbos758.gif
VO = 2 VPP, f = 1 MHz
Figure 76. Harmonic Distortion vs Supply Voltage
THS6214 G078_sbos758.gif
VO = 2 VPP, f = 1 MHz
Figure 78. Harmonic Distortion vs Noninverting Gain
THS6214 G069_sbos758.gif
Figure 69. Large-Signal Frequency Response
THS6214 G071_sbos758.gif
Figure 71. Quiescent Current for Low Bias Setting vs RADJ
THS6214 G073_sbos431.gif
RS optimized for 100% bias
Figure 73. Frequency Response vs Capacitive Load
THS6214 G075_sbos758.gif
f = 1 MHz
Figure 75. Harmonic Distortion vs Output Voltage
THS6214 G077_sbos758.gif
VO = 2 VPP, f = 1 MHz
Figure 77. Harmonic Distortion vs Load Resistance
THS6214 G079_sbos758.gif
Figure 79. Two-Tone, Third-Order Intermodulation Intercept