SBOS974F August   2019  – December 2024 THS6222

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics VS = 12 V
    6. 5.6 Electrical Characteristics VS = 32 V
    7. 5.7 Timing Requirements
    8. 5.8 Typical Characteristics: VS = 12 V
    9. 5.9 Typical Characteristics: VS = 32 V
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Common-Mode Buffer
      2. 6.3.2 Thermal Protection and Package Power Dissipation
      3. 6.3.3 Output Voltage and Current Drive
      4. 6.3.4 Breakdown Supply Voltage
      5. 6.3.5 Surge Test Results
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Broadband PLC Line Driving
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curve
    3. 7.3 Best Design Practices
      1. 7.3.1 Do
      2. 7.3.2 Do Not
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
        1. 7.5.1.1 Wafer and Die Information
      2. 7.5.2 Layout Examples
  9. 8 Device and Documentation Support
    1. 8.1 Development Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGT|16
  • YS|0
  • RHF|24
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics VS = 12 V

at TA ≈ 25°C, differential closed-loop gain (AV) = 10 V/V, differential load (RL) = 50 Ω, series isolation resistor (RS) = 2.5 Ω each, RF = 1.24 kΩ, RADJ = 0 Ω, VCM = open, VO = D1_OUT – D2_OUT, and full bias (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AC PERFORMANCE
SSBW Small-signal bandwidth AV = 5 V/V, RF = 1.5 kΩ, VO = 2 VPP 250 MHz
AV = 10 V/V, RF = 1.24 kΩ, VO = 2 VPP 180
AV = 15 V/V, RF = 1 kΩ, VO = 2 VPP 165
0.1-dB bandwidth flatness 17 MHz
LSBW Large-signal bandwidth VO = 16 VPP 195 MHz
SR Slew rate (20% to 80%) VO = 16-V step 5500 V/µs
Rise and fall time (10% to 90%) VO = 2 VPP 2.1 ns
HD2 2nd-order harmonic distortion AV = 10 V/V,
VO = 2 VPP,
RL = 50 Ω		 Full bias, f = 1 MHz –80 dBc
Mid bias, f = 1 MHz –78
Low bias, f = 1 MHz –78
Full bias, f = 10 MHz –61
Mid bias, f = 10 MHz –61
Low bias, f = 10 MHz –61
HD3 3rd-order harmonic distortion AV = 10 V/V,
VO = 2 VPP,
RL = 50 Ω		 Full bias, f = 1 MHz –90 dBc
Mid bias, f = 1 MHz –86
Low bias, f = 1 MHz –83
Full bias, f = 10 MHz –69
Mid bias, f = 10 MHz –65
Low bias, f = 10 MHz –62
en Differential input voltage noise f ≥ 1 MHz, input-referred, with and without 100 nF noise-decoupling capacitor on VCM pin 2.5 nV/√Hz
in+ Noninverting input current noise f ≥ 1 MHz, each amplifier 1.4 pA/√Hz
in- Inverting input current noise f ≥ 1 MHz, each amplifier 18 pA/√Hz
DC PERFORMANCE
ZOL Open-loop transimpedance gain 1300 kΩ
Input offset voltage (each amplifier) ±12 mV
TA = –40°C ±16
TA = 85°C ±11
Noninverting input bias current ±1 µA
TA = –40°C ±1
TA = 85°C ±1
Inverting input bias current ±8 µA
TA = –40°C ±7
TA = 85°C ±4
INPUT CHARACTERISTICS
Common-mode input voltage Each input with respect to midsupply ±3.0 V
CMRR Common-mode rejection ratio Each input 64 dB
TA = –40°C 67
TA = 85°C 62
Noninverting differential input resistance 10 || 2 kΩ || pF
Inverting input resistance 43 Ω
COMMON-MODE BUFFER CHARACTERISTICS
VCM-OS Common-mode offset voltage Voltage at VCM with respect to midsupply ±2.5 mV
TA = –40°C ±5
TA = 85°C ±1
Common-mode voltage noise With and without 100-nF VCM noise-decoupling capacitor, f ≥ 50 kHz 20 nV/√Hz
Common-mode output resistance f = DC AC-coupled inputs 650 Ω
DC-coupled inputs 520 Ω
OUTPUT CHARACTERISTICS
VO Output voltage swing RL = 100 Ω, RS = 0 Ω ±9.7 V
RL = 50 Ω, RS = 0 Ω ±9.3
RL = 25 Ω, RS = 0 Ω ±8.4
IO Output current (sourcing and sinking) RL = 25 Ω, RS = 0 Ω, based on VO specification ±338 mA
Short-circuit output current ±0.81 A
ZO Closed-loop output impedance f = 1 MHz, differential 0.03 Ω
POWER SUPPLY
DGND DGND pin voltage VS– 0 VS+ – 5 V
IS+ Quiescent current Full bias (BIAS-1 = 0, BIAS-2 = 0) 19.5 mA
Mid bias (BIAS-1 = 1, BIAS-2 = 0) 15
Low bias (BIAS-1 = 0, BIAS-2 = 1) 10.4
Bias off (BIAS-1 = 1, BIAS-2 = 1) 1.1
IS– Quiescent current Full bias (BIAS-1 = 0, BIAS-2 = 0) 18.8 mA
Mid bias (BIAS-1 = 1, BIAS-2 = 0) 14.4
Low bias (BIAS-1 = 0, BIAS-2 = 1) 9.8
Bias off (BIAS-1 = 1, BIAS-2 = 1) 0.4
Current through DGND pin Full bias (BIAS-1 = 0, BIAS-2 = 0) 0.8 mA
+PSRR Positive power-supply rejection ratio Differential 83 dB
–PSRR Negative power-supply rejection ratio Differential 83 dB
BIAS CONTROL
Bias control pin voltage With respect to DGND,
TA = –40°C to +85°C		 0 3.3 12 V
Bias control pin logic threshold Logic 1, with respect to DGND,
TA = –40°C to +85°C		 2.1 V
Logic 0, with respect to DGND,
TA = –40°C to +85°C		 0.8
Bias control pin current(1) BIAS-1, BIAS-2 = 0.5 V (logic 0) –9.6 µA
BIAS-1, BIAS-2 = 3.3 V (logic 1) 0.3 1
Open-loop output impedance Off bias (BIAS-1 = 1, BIAS-2 = 1) 70 || 5 MΩ || pF
(1) Current is considered positive out of the pin.