SBOSAI6 June   2024 THS6232

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics VS = 12V
    6. 5.6 Electrical Characteristics VS = 40V
    7. 5.7 Timing Requirements
    8. 5.8 Typical Characteristics VS = 12V
    9. 5.9 Typical Characteristics VS = 40V
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Common-Mode Buffer
      2. 6.3.2 Thermal Protection and Package Power Dissipation
      3. 6.3.3 Output Voltage and Current Drive
      4. 6.3.4 Breakdown Supply Voltage
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Broadband PLC Line Driving
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curve
    3. 7.3 Best Design Practices
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Examples
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RHF|24
Thermal pad, mechanical data (Package|Pins)

5.8 Typical Characteristics VS = 12V

at TA ≅ 25°C, AV = 10V/V, RF = 1.24kΩ, RL = 50Ω, RS = 2.5Ω, RADJ = 0Ω, and full-bias mode, RF = 2kΩ for ultra-low-bias mode(unless otherwise noted)

THS6232 Small-Signal Frequency Response
VO = 2VPP
Figure 5-1 Small-Signal Frequency Response
THS6232 Out-of-Band Suppression
SGCC HPLC profile, full-bias mode
Figure 5-3 Out-of-Band Suppression
THS6232 Out-of-Band Suppression
SGCC HPLC profile, low-bias mode
Figure 5-5 Out-of-Band Suppression
THS6232 Small-Signal Frequency Response vs RF
AV = 10V/V, VO = 2VPP
Figure 5-7 Small-Signal Frequency Response vs RF
THS6232 Large-Signal Frequency Response vs VO
AV = 10V/V
Figure 5-9 Large-Signal Frequency Response vs VO
THS6232 Small-Signal Frequency Response vs Bias Modes
AV = 10V/V, VO = 2VPP
Figure 5-11 Small-Signal Frequency Response vs Bias Modes
THS6232 Large-Signal Frequency Response vs Bias Modes
AV = 10V/V, VO = 16VPP
Figure 5-13 Large-Signal Frequency Response vs Bias Modes
THS6232 Harmonic Distortion vs Frequency
VO = 2VPP
Figure 5-15 Harmonic Distortion vs Frequency
THS6232 Harmonic Distortion vs VO
f = 10MHz, AV = 10V/V
Figure 5-17 Harmonic Distortion vs VO
THS6232 Large-Signal Pulse Response
VO step = 16VPP
Figure 5-19 Large-Signal Pulse Response
THS6232 Open-Loop Transimpedance Gain and Phase vs Frequency
Midbias simulation
Figure 5-21 Open-Loop Transimpedance Gain and Phase vs Frequency
THS6232 Open-Loop Transimpedance Gain and Phase vs Frequency
Ultra-low-bias simulation
Figure 5-23 Open-Loop Transimpedance Gain and Phase vs Frequency
THS6232 Mode Transition Voltage Threshold
VS = ±6V, DGND = VS–
B1 = full-bias to mid-bias transition with B2 = DGND,
B2 = full-bias to low-bias transition with B1 = DGND
Figure 5-25 Mode Transition Voltage Threshold
THS6232 Large-Signal Frequency Response
VO = 16VPP
Figure 5-2 Large-Signal Frequency Response
THS6232 Out-of-Band Suppression
SGCC HPLC profile, mid-bias mode
Figure 5-4 Out-of-Band Suppression
THS6232 Out-of-Band Suppression
SGCC HPLC profile, ultra-low-bias mode
Figure 5-6 Out-of-Band Suppression
THS6232 Small-Signal Frequency Response vs RF
AV = 15V/V, VO = 2VPP
Figure 5-8 Small-Signal Frequency Response vs RF
THS6232 Large-Signal Frequency Response vs VO
AV = 15V/V
Figure 5-10 Large-Signal Frequency Response vs VO
THS6232 Small-Signal Frequency Response vs Bias Modes
AV = 15V/V, VO = 2VPP
Figure 5-12 Small-Signal Frequency Response vs Bias Modes
THS6232 Large-Signal Frequency Response vs Bias Modes
AV = 15V/V, VO = 16VPP
Figure 5-14 Large-Signal Frequency Response vs Bias Modes
THS6232 Harmonic Distortion vs VO
f = 1MHz, AV = 10V/V
Figure 5-16 Harmonic Distortion vs VO
THS6232 Small-Signal Pulse Response
VO step = 2VPP
Figure 5-18 Small-Signal Pulse Response
THS6232 Open-Loop Transimpedance Gain and Phase vs Frequency
Full-bias simulation
Figure 5-20 Open-Loop Transimpedance Gain and Phase vs Frequency
THS6232 Open-Loop Transimpedance Gain and Phase vs Frequency
Low-bias simulation
Figure 5-22 Open-Loop Transimpedance Gain and Phase vs Frequency
THS6232 Open-Loop Output Impedance vs Frequency
Simulation
Figure 5-24 Open-Loop Output Impedance vs Frequency