SBOSAI6 June   2024 THS6232

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics VS = 12V
    6. 5.6 Electrical Characteristics VS = 40V
    7. 5.7 Timing Requirements
    8. 5.8 Typical Characteristics VS = 12V
    9. 5.9 Typical Characteristics VS = 40V
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Common-Mode Buffer
      2. 6.3.2 Thermal Protection and Package Power Dissipation
      3. 6.3.3 Output Voltage and Current Drive
      4. 6.3.4 Breakdown Supply Voltage
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Broadband PLC Line Driving
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curve
    3. 7.3 Best Design Practices
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Examples
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RHF|24
Thermal pad, mechanical data (Package|Pins)

4 Pin Configuration and Functions

Figure 4-1 RHF Package, 24-Pin VQFN With Exposed Thermal Pad (Top View)
Table 4-1 Pin Functions
PIN TYPE DESCRIPTION
NAME NO.
BIAS-1(1) 23 Input Bias mode control pin 1. See Table 4-2 for more details.
BIAS-2(1) 24 Input Bias mode control pin 2. See Table 4-2 for more details.
D1_IN– 19 Input Amplifier D1 inverting input
D1_IN+ 1 Input Amplifier D1 noninverting input
D1_OUT 20 Output Amplifier D1 output
D2_IN– 18 Input Amplifier D2 inverting input
D2_IN+ 2 Input Amplifier D2 noninverting input
D2_OUT 17 Output Amplifier D2 output
DGND(2) 3 Input Ground reference for bias control pins
IADJ 4 Input Bias current adjustment pin
NC 5-16 — No internal connection
VS– 22 — Negative power-supply connection
VS+ 21 — Positive power-supply connection
Thermal Pad Pad — Electrically connected to die substrate and VS–.
Connect to VS– on the printed circuit board (PCB) for best performance.
(1) The THS6232 defaults to the shutdown (disable) state if a signal is not present on the bias pins.
(2) The DGND pin ranges from VS– to (VS+) – 5V.
Table 4-2 Bias Mode Logic Table
BIAS CONTROL PINS MODE TEST CONDITIONS (AV = 10V/V, 50Ω LOAD)
BIAS-1 BIAS-2
0 0 Full bias RF = 1.24kΩ, RG = 274Ω
1 0 Mid bias RF = 1.24kΩ, RG = 274Ω
0 1 Low bias RF = 1.24kΩ, RG = 274Ω
0 (IADJ = float) 1 (IADJ = float) Ultra low bias RF = 2kΩ, RG = 442Ω
1 1 Shutdown