SBOSAI6 June   2024 THS6232

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics VS = 12V
    6. 5.6 Electrical Characteristics VS = 40V
    7. 5.7 Timing Requirements
    8. 5.8 Typical Characteristics VS = 12V
    9. 5.9 Typical Characteristics VS = 40V
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Common-Mode Buffer
      2. 6.3.2 Thermal Protection and Package Power Dissipation
      3. 6.3.3 Output Voltage and Current Drive
      4. 6.3.4 Breakdown Supply Voltage
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Broadband PLC Line Driving
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curve
    3. 7.3 Best Design Practices
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Examples
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RHF|24
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.6 Electrical Characteristics VS = 40V

at TA ≅ 25°C, differential closed-loop gain (AV) = 10V/V, differential load (RL) = 100Ω, RF = 1.24kΩ, RADJ = 0Ω, VO = D1_OUT – D2_OUT, and full bias (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AC PERFORMANCE
SSBW Small-signal bandwidth AV = 5V/V, RF = 1.5kΩ, VO = 2VPP 60 MHz
AV = 10V/V, RF = 1.24kΩ, VO = 2VPP 50
AV = 15V/V, RF = 1kΩ, VO = 2VPP 45
0.1dB bandwidth flatness 2 MHz
LSBW Large-signal bandwidth VO = 16VPP 41 MHz
SR Slew rate (20% to 80%) VO = 16V step 1200 V/µs
Rise and fall time (10% to 90%) VO = 2VPP 5 ns
HD2 2nd-order harmonic distortion AV = 10V/V,
VO = 2VPP,
RL = 100Ω		 Full bias, f = 1MHz –101 dBc
Mid bias, f = 1MHz  –96
Low bias, f = 1MHz –93
Ultra-low bias, f = 1MHz –93
Full bias, f = 10MHz –71
Mid bias, f = 10MHz –65
Low bias, f = 10MHz –63
Ultra-low bias, f = 10MHz –57
HD3 3rd-order harmonic distortion AV = 10V/V,
VO = 2VPP,
RL = 100Ω		 Full bias, f = 1MHz –115 dBc
Mid bias, f = 1MHz  –105
Low bias, f = 1MHz –98
Ultra-low bias, f = 1MHz –84
Full bias, f = 10MHz –77
Mid bias, f = 10MHz –67
Low bias, f = 10MHz –60
Ultra-low bias, f = 10MHz –50
en Differential input voltage noise f ≥ 1MHz, input-referred 5 nV/√Hz
in+ Noninverting input current noise f ≥ 1MHz, each amplifier 53 pA/√Hz
in– Inverting input current noise f ≥ 1MHz, each amplifier 235 pA/√Hz
DC PERFORMANCE
ZOL Open-loop transimpedance gain 4 GΩ
Input offset voltage (each amplifier) ±7 mV
Input offset voltage matching Amplifier A to B ±0.6 mV
Noninverting input bias current ±60 µA
Inverting input bias current ±100 µA
INPUT CHARACTERISTICS
Common-mode input voltage Each input with respect to midsupply ±15 V
CMRR Common-mode rejection ratio Each input 79 dB
Noninverting differential input impedance 10 || 1.5 kΩ || pF
Inverting input resistance 85 Ω
OUTPUT CHARACTERISTICS
VO
Output voltage swing

 RL = 100Ω, RS = 0Ω ±35 V
RL = 50Ω, RS = 0Ω ±25.5
RL = 25Ω, RS = 0Ω ±14.5
IO Output current (sourcing and sinking) RL = 25Ω, RS = 0Ω, based on VO specification +680/–530 mA
Short-circuit output current 0.8 A
ZO Closed-loop output impedance f = 1MHz, differential 0.017 Ω
POWER SUPPLY
IS+ Quiescent current Full bias (BIAS-1 = 0, BIAS-2 = 0) 26 mA
Mid bias (BIAS-1 = 1, BIAS-2 = 0) 21
Low bias (BIAS-1 = 0, BIAS-2 = 1) 16
Ultra-low bias (BIAS-1 = 0, BIAS-2 = 1, IADJ = float) 11
Bias off (BIAS-1 = 1, BIAS-2 = 1) 0.75
Current through DGND pin Full bias (BIAS-1 = 0, BIAS-2 = 0) 0.15 mA
+PSRR Positive power-supply rejection ratio Differential 91 dB
–PSRR Negative power-supply rejection ratio Differential 91 dB
BIAS CONTROL
Bias control pin voltage  With respect to DGND,
 0 3.3 Vs+ V
Bias control pin logic threshold Logic 1, with respect to DGND,
 2.1 V
Logic 0, with respect to DGND,
 0.8
Bias control pin current(1) BIAS-1, BIAS-2 = 0.5V (logic 0) –7 µA
Bias control pin current(1) BIAS-1, BIAS-2 = 3.3V (logic 1) 6 nA
Open-loop output impedance Off bias (BIAS-1 = 1, BIAS-2 = 1) 245 || 17 MΩ || pF
(1) Current is considered positive into the pin.