5.1.1 Interpolating Finite Impulse Responses Filter (IFIR)

The interpolating FIR is used to upsample the input data by 2x. In the THS8200 there are five IFIRs. The first two are used only when the input data is in 4:2:2 format for conversion to a 4:4:4 internal representation on both color difference channels. The last three IFIRs are used to upsample the internal data to the DACs on all three channels in case 2x video interpolation is enabled. By 2x oversampling the video data, the requirements for the analog reconstruction filter at the DAC outputs are relaxed so it can be built with fewer components, thereby also improving the overall video frequency characteristic (less group delay variation). All of the IFIRs can be bypassed or switched in by programming the appropriate I²C registers. The coefficients of all IFIRs are fixed.

5.1.2 Color-Space Conversion (CSC)

The color-space converter block is used to convert input video data in one type of color space to output video data in another color space (for example, RGB to YCbCr, or YCbCr to RGB). This block contains a 3×3 matrix multiplier/adder and a 3×1 adder. All multiplier and adder coefficients can be programmed through the I²C interface to support any linear matrixing+offset operation on the video data.

5.1.3 Clip/Shift/Multiplier (CSM)

The clip-shift-multiply block optionally clips the input code range at a programmed low/high code, shifts the input video data downwards, and multiplies the input by a programmable coefficient in the range 0−1.999. This allows for operation with a reduced input code range such as prescribed in the ITU-R.BT601 recommendation. Each channel can be independently programmed to accommodate different digital ranges for each of the three input channels. For example, for standard video signals the Y channel has a digital input range of 64−940, whereas the two other channels have an input range of 64−960. All three channels must have a DAC output range of 0−700 mV, so normally the analog voltage corresponding to 1 LSB would have to change to account for the different digital inputs. This might cause matching errors. Therefore in the THS8200 the DAC LSB does not change; rather LSB conversion is done by scaling the digital inputs to the DAC's full input range. Furthermore, the CSM output is 11 bits wide and is sent to the 11-bit DACs. The extra bit of resolution resolves nonlinearities introduced by the scaling process. The clipping function can be switched off to allow for super-white/super-black excursions.

5.1.4 Digital Multiplexer (DIGMUX)

This multiplexer in front of the DACs can select between video signals at 1x or 2x the pixel clock rate. It is also used to switch in blanking/sync level data generated by the display timing generator (DTG) block and test pattern data (for example, color bars, I²C-controlled DAC levels) or to perform data insertion (CGMS) during vertical blanking.

5.1.5 Display Timing Generator (DTG)

The display timing generator is responsible for the generation of the correct frame format including all sync, equalization and serration pulses. In master timing mode, the DTG is synchronized to external synchronization inputs, either from the dedicated device terminals HS_IN, VS_IN, and FID or is synchronized to the identifiers extracted from the input data stream, as selected by the DMAN mode. In master timing mode, the DTG generates the required field/frame format based on the externally applied pixel clock input.

When active data is not being passed to the DACs, that is, during the horizontal/vertical blanking intervals, the DTG generates the correct digital words for blank, sync levels and other level excursions, such as pre- and post-serration pulses and equalization pulses.

Horizontal timings, as well as amplitudes of negative and positive sync, HDTV broad pulses and SDTV pre- and post-equalization and serration pulses, are all I²C-programmable to accommodate, for example, the generation of both EIA.770-1 (10:4 video/sync ratio) and EIA.770-2 (7:3 video/sync ratio) compliant analog component video outputs, and to support nonstandard video timing formats.

In addition or as an alternative to the composite sync inserted on green/luma channel or all analog outputs, output video timing can be carried by dedicated Hsync/Vsync output signals as well. The position, duration and polarity of Hsync and Vsync outputs are fully programmable to support, for example, the centering of the active video window within the picture frame.

The DTG also controls the data multiplexer in the DIGMUX block. DIGMUX can be programmed to pass device input data only on active video lines (inserting DTG-generated blanking level during blanking intervals). Alternatively, the DTG can pass device input data also during some VBI lines (ancillary data in the input stream is passed transparently on some VBI lines). Finally, the device can also generate its own ancillary data and insert it into the analog outputs according to the CGMS data format for the 525P video format.

5.1.6 Clock Generator (CGEN)

The clock generator is an analog delay-locked loop (DLL) based circuit and provides a 2x clock from the CLKIN input. The 2x clock is used by the CDRV block for 2x video interpolation. Some video formats also require a 1/2 rate clock used for 4:2:2 to 4:4:4 conversion.

5.1.7 Clock Driver (CDRV)

The clock drive block generates all on-chip clocks. Its inputs are control signals from the digital logic, the original CLKIN, and the 2x clock from CGEN. Outputs include a half-rate clock, full-rate clock, and a 2x full-rate clock. The clocks are used for both optional on-chip interpolation processes: 4:2:2 to 4:4:4 interpolation and 1x to 2x video oversampling.

5.1.8 I²C Host Interface (I2CSLAVE)

The I²C interface controls and programs the internal I²C registers. The THS8200 I²C interface implementation supports the fast I²C specification (SCL: 400 kHz) and allows the writing and reading of registers. An auto-increment addressing feature simplifies block register programming. The I²C interface works without a clock present on CLKIN.

5.1.9 Test Block (TST)

The test block controls all the test functions of the THS8200. In addition to manufacturing test modes, this block contains several user test modes including a DAC internal ramp generator and a 75% SMPTE video color bar generator.

5.1.10 D/A Converters (DACs)

THS8200 contains three DACs operating at up to 205 MSPS and with an internal resolution of 11 bits. Each DAC contains an integrated video sync inserter. The syncs are inserted by means of additional current source circuits either on the green/luma (Y) channel only or on all the DAC output channels, to be compliant with both consumer (EIA, sync-on-G/Y) as well as professional (SMPTE, sync-on-all) standards.

The DAC speed supports all ATSC formats, including 1080p, as well as all PC graphics (VESA) formats up to UXGA at 75 Hz (202.5 MSPS).