SLLSFN8 September   2023 THVD1330

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Data Rate and Bus Length
        2. 9.2.1.2 Stub Length
        3. 9.2.1.3 Bus Loading
        4. 9.2.1.4 Receiver Failsafe
        5. 9.2.1.5 Transient Protection
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Device Support
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Parameter Measurement Information

GUID-D7ACE0D8-1357-42A6-91F8-343E21A7575D-low.gif Figure 7-1 Measurement of Driver Differential Output Voltage With Common-Mode Load
GUID-608B44E9-16F5-4A52-BAF0-EC32E3D17AAB-low.gif Figure 7-2 Measurement of Driver Differential and Common-Mode Output With RS-485 Load
GUID-42D50075-2C16-41DE-944E-E5F63BBF53FA-low.gif
Generator: PRR = 500 kHz, 50% Duty Cycle, tr < 60 ns, tf < 6 ns ZO = 50 Ω
Figure 7-3 Driver Switching Test Circuit and Voltage Waveforms
GUID-7A91C788-A3A3-4F4B-80D3-FE1C55B16C66-low.gif
Generator: PRR = 500 kHz, 50% Duty Cycle, tr < 60 ns, tf < 6 ns ZO = 50 Ω
Figure 7-4 Driver High-Level Enable and Disable Time Test Circuit and Voltage Waveforms
GUID-BB60A67A-4C88-4BB7-AA1A-41933D04B090-low.gif
Generator: PRR = 500 kHz, 50% Duty Cycle, tr < 60 ns, tf < 6 ns ZO = 50 Ω
Figure 7-5 Driver Low-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms
GUID-6BDD57DB-6BC1-4517-97B5-13C05AF2D197-low.gif Figure 7-6 Receiver Switching Test Circuit and Voltage Waveforms
GUID-F5F1155A-D51E-40D0-B406-941FC760589B-low.gif Figure 7-7 Receiver Enable and Disable Time Test Circuit and Voltage Waveforms With Drivers Enabled
GUID-3557DFCD-E407-4B45-875F-EC81E8815547-low.gif Figure 7-8 Receiver Enable Time From Standby (Driver Disabled)