SLLSFQ4A September   2022  – March 2023 THVD1424

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  ESD Ratings [IEC]
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Power Dissipation
    7. 6.7  Electrical Characteristics
    8. 6.8  Switching Characteristics_500 kbps
    9. 6.9  Switching Characteristics_20 Mbps
    10. 6.10 Switching Characteristics_Termination resistor
    11. 6.11 Switching Characteristics_Duplex switching
    12. 6.12 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 On-Chip Switchable Termination
      2. 8.4.2 Operational Data rate
      3. 8.4.3 Protection Features
  9. 9 Application Information Disclaimer
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Data Rate and Bus Length
        2. 9.2.1.2 Stub Length
        3. 9.2.1.3 Bus Loading
        4. 9.2.1.4 Receiver Failsafe
        5. 9.2.1.5 Transient Protection
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

GUID-20220801-CA0I-4SJ5-LGMS-RNNKLTG8JGRG-low.svg Figure 5-1 VQFN (RGT) Package, 16-Pins
(Top View)
Table 5-1 Pin Functions
PIN TYPE DESCRIPTION
NAME NO.
R 1 Digital output Logic output RS485 data
RE 2 Digital input Receiver enable/disable. Internal pull-up. Receiver disabled by default
DE 3 Digital input Driver enable/disable. Internal pull-down. Driver disabled by default
D 4 Digital input Logic input RS485 data. Internal pull-up. Drives the bus high by default if driver is enabled
TERM_TX 5 Digital input 120 Ω on-chip termination control for Y/Z pins. Internal pull-down. Termination across Y/Z is disabled by default
GND 6 GND Ground
TERM_RX 7 Digital input 120 Ω on-chip termination control for A/B pins. Internal pull-down. Termination across A/B is disabled by default
SLR 8 Digital input Slew rate control. Internal pull-down, default 20 Mbps operation. Logic high SLR enables slow speed (500 kbps)
Y 9 Bus input/output RS485 bus pins. In full duplex, this pin is non-inverting driver output. In half duplex, this is non-inverting driver output and non-inverting receiver input
Z 10 Bus input/output RS485 bus pins. In full duplex, this pin is inverting driver output. In half duplex, this is inverting driver output and inverting receiver input
B 11 Bus input RS485 receiver inverting input pin in full duplex mode
A 12 Bus input RS485 receiver non-inverting input pin in full duplex mode
VIO 13 Supply 1.65 to 5.5 V logic supply voltage
VCC 14 Supply 3 to 5.5V supply voltage
H/F 15 Digital input Half to full duplex control. Internal pull-down, so full duplex by default- Y/Z are driver output, A/B are receiver input pins
NC 16 No connect Not connected internally
Thermal pad -- Connect to GND for optimal thermal and electrical performance