SLLSFQ4A September   2022  – March 2023 THVD1424

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  ESD Ratings [IEC]
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Power Dissipation
    7. 6.7  Electrical Characteristics
    8. 6.8  Switching Characteristics_500 kbps
    9. 6.9  Switching Characteristics_20 Mbps
    10. 6.10 Switching Characteristics_Termination resistor
    11. 6.11 Switching Characteristics_Duplex switching
    12. 6.12 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 On-Chip Switchable Termination
      2. 8.4.2 Operational Data rate
      3. 8.4.3 Protection Features
  9. 9 Application Information Disclaimer
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Data Rate and Bus Length
        2. 9.2.1.2 Stub Length
        3. 9.2.1.3 Bus Loading
        4. 9.2.1.4 Receiver Failsafe
        5. 9.2.1.5 Transient Protection
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Parameter Measurement Information

GUID-20220729-SS0I-XLVQ-B0D5-R6DQGW9RRZ5S-low.svg Figure 7-1 Measurement of Driver Differential Output Voltage With Common-Mode Load
GUID-20220729-SS0I-FFGF-0RTV-S4SLJX6JMSGZ-low.svg Figure 7-2 Measurement of Driver Differential and Common-Mode Output With RS-485 Load
GUID-20220729-SS0I-XHQ9-BWPN-FFWRPBM7TZ18-low.svg Figure 7-3 Measurement of Driver Differential Output Rise and Fall Times and Propagation Delays
GUID-20220729-SS0I-FW2R-1VWG-CTPLL7SWQQLV-low.svg Figure 7-4 Measurement of Driver Enable and Disable Times With Active High Output and Pull-Down Load
GUID-20220729-SS0I-FRHK-KCF9-NNTV2BBWRKQH-low.svg Figure 7-5 Measurement of Driver Enable and Disable Times With Active Low Output and Pull-up Load
GUID-D106FD23-B6C1-4EB4-B1C3-5B45471F547C-low.gifFigure 7-6 Measurement of Receiver Output Rise and Fall Times and Propagation Delays
GUID-20220729-SS0I-FBGD-RFPD-SNBNH075HMVQ-low.svg Figure 7-7 Measurement of Receiver Enable/Disable Times With Driver Enabled
GUID-20220729-SS0I-QFLK-RQVR-GPP3N8GHKVB6-low.svg Figure 7-8 Measurement of Receiver Enable Times With Driver Disabled
GUID-20220729-SS0I-Q7CF-RLFT-CT3M29JRFQ9F-low.svg Figure 7-9 Measurement of Enable and Disable times of Driver Terminal Termination Resistor
GUID-20220729-SS0I-KRSW-NJKX-CVMLKW0R3C0S-low.svg Figure 7-10 Measurement of Enable and Disable times of Receiver Terminal Termination Resistor
GUID-20220729-SS0I-3FXL-7HTS-B0WPDZ7RDDJP-low.svg Figure 7-11 Measurement of Time to Switch from Half duplex mode to Full duplex mode and vice versa