SLLSFQ4A September   2022  – March 2023 THVD1424

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  ESD Ratings [IEC]
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Power Dissipation
    7. 6.7  Electrical Characteristics
    8. 6.8  Switching Characteristics_500 kbps
    9. 6.9  Switching Characteristics_20 Mbps
    10. 6.10 Switching Characteristics_Termination resistor
    11. 6.11 Switching Characteristics_Duplex switching
    12. 6.12 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 On-Chip Switchable Termination
      2. 8.4.2 Operational Data rate
      3. 8.4.3 Protection Features
  9. 9 Application Information Disclaimer
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Data Rate and Bus Length
        2. 9.2.1.2 Stub Length
        3. 9.2.1.3 Bus Loading
        4. 9.2.1.4 Receiver Failsafe
        5. 9.2.1.5 Transient Protection
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.4.1 On-Chip Switchable Termination

THVD1424 has 2 termination resistors of nominal 120 Ω, one across Y/Z and another across A/B. Both termination resistors are enabled or disabled using pins as described in On-chip termination function table. Both the termination resistors can be enabled or disabled independent of the state of driver or receiver. Termination is OFF if the device is unpowered or in thermal shutdown.

Table 8-4 On-chip termination function table
Signal state Device mode Function Comments
TERM_TX = VIO Full duplex mode 120 Ω enabled between Y and Z Termination between Y/Z is disabled by default
TERM_TX = GND or floating Full duplex mode 120 Ω disabled between Y and Z
TERM_RX = VIO Full duplex mode 120 Ω enabled between A and B Termination between A/B is disabled by default
TERM_RX = GND or floating Full duplex mode 120 Ω disabled between A and B
TERM_RX = X, TERM_TX = VIO Half duplex mode 120 Ω enabled between Y and Z In half duplex mode, TERM_RX is don't care and TERM_TX has higher priority
TERM_RX = X, TERM_TX = GND Half duplex mode 120 Ω disabled between Y and Z

On-chip 120 Ω termination resistor variation with temperature and across common mode voltage is shown in following images.

GUID-20220915-SS0I-WD7H-L4ZT-RBKBTMRXDSXK-low.svgFigure 8-1 Termination resistor vs Temperature
GUID-20220915-SS0I-4NVC-TDRR-BPZ1WWXBTJB1-low.svgFigure 8-2 Termination resistor vs Bus common mode voltage

THVD1424 on-chip termination resistor has been designed so the termination block offers a resistive load to the bus, and does not alter the magnitude or phase of the bus signals from DC to 20 Mbps signaling. See the following images with the bus voltage swept from -6 V to +6 V. Current into the bus changes linearly in both conditions of termination ON or OFF.

GUID-20220915-SS0I-LHZG-4F9J-KV2WRQPMHQD1-low.svgFigure 8-3 Voltage vs Current across AB bus pins with termination OFF
GUID-20220915-SS0I-W2GC-3NHD-M5TLNT9W0RKH-low.svgFigure 8-4 Voltage vs Current across AB bus pins with termination ON