SLLSFQ4A September   2022  – March 2023 THVD1424

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  ESD Ratings [IEC]
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Power Dissipation
    7. 6.7  Electrical Characteristics
    8. 6.8  Switching Characteristics_500 kbps
    9. 6.9  Switching Characteristics_20 Mbps
    10. 6.10 Switching Characteristics_Termination resistor
    11. 6.11 Switching Characteristics_Duplex switching
    12. 6.12 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 On-Chip Switchable Termination
      2. 8.4.2 Operational Data rate
      3. 8.4.3 Protection Features
  9. 9 Application Information Disclaimer
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Data Rate and Bus Length
        2. 9.2.1.2 Stub Length
        3. 9.2.1.3 Bus Loading
        4. 9.2.1.4 Receiver Failsafe
        5. 9.2.1.5 Transient Protection
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.4.3 Protection Features

THVD1424 has in-built protection features such as supply undervoltage, bus short circuit and thermal shutdown.

Supply undervoltage protection is present on both VCC and VIO supplies. This maintains the bus output and receiver logic output in known driven state when both the supplies are above their rising undervoltage thresholds. Table below describes the device behavior in various scenarios of supply levels.

Table 8-6 Supply Function Table
VCC VIO Driver Output Receiver Output Termination across bus pins YZ and AB
> UVVCC(rising) > UVVIO(rising) Determined by DE and D inputs Determined by RE and A-B Determined by TERM_TX and TERM_RX pins
< UVVCC(falling) > UVVIO(rising) High impedance Undetermined OFF
> UVVCC(rising) < UVVIO(falling) High impedance High impedance Undetermined
< UVVCC(falling) < UVVIO(falling) High impedance High impedance OFF

Bus terminals are protected against high voltage short circuit events up to ± 16 V. Additionally, bus short circuit current is limited to 250 mA. So in events like bus contention when multiple drivers are driving the bus simultaneously, the current through the bus terminals is internally limited. If the power dissipation makes the junction temperature cross 150 °C, thermal shutdown is activated which disables the driver and receiver and reduces the on-chip power dissipation. The device is enabled once the junction temperature falls by the thermal shutdown hysteresis as specified in electrical parameter section of the data sheet.