SLLSF79B April   2021  – September 2021 THVD1439 , THVD1439V , THVD1449 , THVD1449V

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  ESD Ratings, IEC
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Power Dissipation
    7. 6.7  Electrical Characteristics
    8. 6.8  Switching Characteristics (THVD1439, THVD1439V)
    9. 6.9  Switching Characteristics (THVD1449, THVD1449V)
    10. 6.10 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Electrostatic Discharge (ESD) Protection
      2. 8.3.2 Electrical Fast Transient (EFT) Protection
      3. 8.3.3 Surge Protection
      4. 8.3.4 Enhanced Receiver Noise Immunity
      5. 8.3.5 Failsafe Receiver
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Data Rate and Bus Length
        2. 9.2.1.2 Stub Length
        3. 9.2.1.3 Bus Loading
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VCC Supply voltage 3 5.5 V
VIO IO Supply Voltage (V Variant) 1.65 VCC V
VI Input voltage on logic pins (R, D, DE, or RE) THVD1439, THVD1449 0 5.5 V
VI THVD1439V, THVD1449V 0 VIO V
VI Input voltage at bus pins (A or B) (1) -12 12 V
VIH High-level input voltage (R, D, DE, or RE) THVD1439V, THVD1449V 0.67 * VIO VIO V
VIL Low-level input voltage (R, D, DE, or RE) 0 0.33 * VIO V
VIH High-level input voltage (R, D, DE, or RE) THVD1439, THVD1449 2 5.5 V
VIL Low-level input voltage (R, D, DE, or RE) 0 0.8 V
VID Differential input voltage -12 12 V
IO Output current, driver -60 60 mA
IOR Output current, receiver -8 8 mA
RL Differential load resistance 54 Ω
1/tUI Signaling rate THVD1439, THVD1439V 250 kbps
THVD1449, THVD14149V 12 Mbps
TA Operating ambient temperature -40 125 °C
(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.