SLLSFQ5A january   2023  – july 2023 THVD1454

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  ESD Ratings [IEC]
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Power Dissipation
    7. 6.7  Electrical Characteristics
    8. 6.8  Switching Characteristics_500 kbps
    9. 6.9  Switching Characteristics_20 Mbps
    10. 6.10 Switching Characteristics_Termination resistor
    11. 6.11 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 On-Chip Switchable Termination
      2. 8.4.2 Operational Data rate
      3. 8.4.3 Protection Features
  10. 9 Application Information Disclaimer
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Data Rate and Bus Length
        2. 9.2.1.2 Stub Length
        3. 9.2.1.3 Bus Loading
        4. 9.2.1.4 Receiver Failsafe
        5. 9.2.1.5 Transient Protection
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.4.1 On-Chip Switchable Termination

THVD1454 has integrated termination resistor of nominal 120 Ω across A/B bus terminals. Termination resistor is enabled or disabled using the TERM pin described in Table 8-3.

Table 8-3 On-chip termination function table
Signal state Function Comments
TERM = VCC 120 Ω enabled between A and B
TERM = GND or floating 120 Ω disabled between A and B Termination is disabled by default

On-chip 120 Ω termination resistor variation with temperature and across common mode voltage is shown in Figure 8-1 and Figure 8-2.

GUID-20220915-SS0I-WD7H-L4ZT-RBKBTMRXDSXK-low.svgFigure 8-1 Termination Resistor vs Temperature
GUID-20220915-SS0I-4NVC-TDRR-BPZ1WWXBTJB1-low.svgFigure 8-2 Termination Resistor vs Bus Common Mode voltage

THVD1454 on-chip termination resistor has been designed so the termination block offers a resistive load to the bus, and does not alter the magnitude or phase of the bus signals from DC to 20Mbps signaling. See Figure 8-3 and Figure 8-4 with the bus voltage swept from -6 V to +6 V. Current into the bus changes linearly in both conditions of termination ON or OFF.

GUID-20220915-SS0I-LHZG-4F9J-KV2WRQPMHQD1-low.svgFigure 8-3 Voltage vs Current Across AB Bus Pins with Termination OFF
GUID-20220915-SS0I-W2GC-3NHD-M5TLNT9W0RKH-low.svgFigure 8-4 Voltage vs Current Across AB Bus Pins with Termination ON