SLLSFQ5A january   2023  – july 2023 THVD1454

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  ESD Ratings [IEC]
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Power Dissipation
    7. 6.7  Electrical Characteristics
    8. 6.8  Switching Characteristics_500 kbps
    9. 6.9  Switching Characteristics_20 Mbps
    10. 6.10 Switching Characteristics_Termination resistor
    11. 6.11 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 On-Chip Switchable Termination
      2. 8.4.2 Operational Data rate
      3. 8.4.3 Protection Features
  10. 9 Application Information Disclaimer
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Data Rate and Bus Length
        2. 9.2.1.2 Stub Length
        3. 9.2.1.3 Bus Loading
        4. 9.2.1.4 Receiver Failsafe
        5. 9.2.1.5 Transient Protection
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.7 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted). All typical values are at 25°C and supply voltage of VCC = 5 V , unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Driver
|VOD| Driver differential output voltage magnitude RL = 60 Ω, –7 V ≤ Vtest ≤ 12 V (See Figure 7-1 ) 1.5 3.3 V
RL = 60 Ω, –7 V ≤ Vtest ≤ 12 V, 4.5 V ≤ VCC ≤ 5.5 V (See Figure 7-1 ) 2.1 3.3 V
RL = 100 Ω (See Figure 7-2 ) 2 4 V
RL = 54 Ω, 4.5 V ≤ VCC ≤ 5.5 V (See Figure 7-2 ) 2.1 3.3 V
RL = 54 Ω (See Figure 7-2 ) 1.5 3.3 V
Δ|VOD| Change in magnitude of differential output voltage RL = 54 Ω or 100 Ω (See Figure 7-2 ) –50 50 mV
VOC Common-mode output voltage RL = 54 Ω or 100 Ω (See Figure 7-2 ) VCC/2 3 V
ΔVOC(SS) Change in steady-state common-mode output voltage RL = 54 Ω or 100 Ω (See Figure 7-2 ) –50 50 mV
IOS Short-circuit output current DE = VIO, -7 V ≤ (VA or VB) ≤ 12 V, or A shorted to B   –250 250 mA
Receiver
II Bus input current (termination disabled) DE = 0 V, VCC = 0 V or 5.5 V VI = 12 V 85 110 μA
VI = –7 V –100 –70 μA
IRXT Receiver bus input leakage current with termination enabled DE = 0 V, VCC = 5.5 V, TERM = VCC VI = - 7 to 12 V -300 300 μA
VTH+ Positive-going input threshold voltage(1) Over common-mode range of - 7 V to 12 V - 85 - 45 mV
VTH- Negative-going input threshold voltage(1) –200 –150 mV
VHYS Input hysteresis 30 50 mV
CA,B Input differential capacitance Measured between A and B, f = 1 MHz 20 pF
VOH Output high voltage IOH = –8 mA VCC – 0.4 VCC – 0.2 V
VOL Output low voltage IOL = 8 mA 0.2 0.4 V
IOZ Output high-impedance current, R pin VO = 0 V or VCC, RE = VCC –2 2 µA
Logic
IIN Input current (D, RE, DE , SLR, TERM) 3 V ≤ VCC ≤ 5.5 V, 0 V ≤ VIN ≤ VCC -5 5 µA
Thermal Protection
TSHDN Thermal shutdown threshold Temperature rising 150 170 °C
THYS Thermal shutdown hysteresis 15 °C
Supply
UVVCC (rising) Rising under-voltage threshold on VCC 2.5 2.7 V
UVVCC (falling) Falling under-voltage threshold on VCC 2 2.1 V
UVVCC(hys) Hysteresis on under-voltage of VCC 400 mV
ICC Supply current (quiescent), VCC = 4.5 V to 5.5 V, TERM = Floating or low, SLR = X Driver and receiver enabled RE = 0 V, DE = VCC, No load 1.5 3 mA
Driver enabled, receiver disabled RE = VCC, DE = VCC, No load 1.3 2.5 mA
Driver disabled, receiver enabled RE = 0 V, DE = 0 V, No load 0.8 1.2 mA
Driver and receiver disabled RE = VCC, DE = 0 V, D = open, No load 0.2 8 µA
ICC Supply current (quiescent), VCC = 3 V to 3.6 V, TERM = Floating or low, SLR = X Driver and receiver enabled RE = 0 V, DE = VCC, No load 1.4 2 mA
Driver enabled, receiver disabled RE = VCC, DE = VCC, No load 1 1.5 mA
Driver disabled, receiver enabled RE = 0 V, DE = 0 V, No load 0.7 1 mA
Driver and receiver disabled RE = VCC, DE = 0 V, D = open, No load 0.2 8 µA
ICCDT Supply current in driver termination mode Driver enabled, receiver disabled with termination ON RE = VCC, DE= VIO, TERM = VCC 39 48 mA
ICCRT Supply current in receiver termination mode Receiver enabled and driver disabled, with termination ON RE = GND, DE = 0 V, TERM = VCC 1 1.3 mA
ICCT Supply current in device disabled, termination enabled mode Driver and Receiver disabled, termination ON RE = VCC, DE = 0 V, TERM = VCC 200 350 µA
On-Chip termination resistor
RTERM 120 Ω termination across receiver output A/B terminals DE = GND, TERM = VCC, VAB = 2 V, VB = -7 V, 0 V, 10 V
See Figure 7-9		 102 120 138 Ω
(1) VTH+ is specified to be at least VHYS higher than VTH–.