SLLSF68 September   2019 THVD1505

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Network Application With Polarity Correction (POLCOR)
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 ESD Ratings [IEC]
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Power Dissipation Characteristics
    8. 6.8 Switching Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Driver
    2. 7.2 Receiver
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Bus Polarity Correction
        1. 8.3.1.1 Passive Polarity Definition Using Fail-Safe Biasing Network
        2. 8.3.1.2 Active Polarity Definition by the Master Node
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Device Configuration
      2. 9.1.2 Bus Design
      3. 9.1.3 Fail-Safe Biasing for Passive Polarity Definition
      4. 9.1.4 Cable Length Versus Data Rate
      5. 9.1.5 Stub Length
      6. 9.1.6 Transient Protection
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Design and Layout Considerations For Transient Protection
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Driver
│VOD│ Driver differential-output voltage magnitude Vtest from –7 to +12 V See Figure 7 1.5 2.5 V
RL = 54 Ω (RS-485), CL = 50 pF See Figure 8 1.5 2.5
RL = 100 Ω (RS-422), CL = 50 pF 2 3
Δ│VOD│ Change in magnitude of driver differential-output voltage RL = 54 Ω, CL = 50 pF See Figure 8 –50 50 mV
VOC(SS) Steady-state common-mode output voltage RL = 54 Ω, CL = 50 pF See Figure 8 1 VCC / 2 3 V
ΔVOC Change in differential driver common-mode output voltage –50 50 mV
VOC(PP) Peak-to-peak driver common-mode output voltage 250 mV
│IOS│ Driver short-circuit output current DE = VCC, -7 V ≤ [VA or VB] ≤ 12 V, or A pin shorted to B pin 150 mA
COD Differential output capacitance 8 pF
Receiver
II Bus input current (driver disabled) DE = 0 V, VCC = 0 V or 5.5 V VI = 12 V 75 110 µA
VI = –7 V –90 –70
RA, RB Bus input impedance VA = -7 V, VB = 12 V and VA = 12 V, VB = -7 V See Figure 12 96 kΩ
VIT+ Positive-going receiver differential-input voltage threshold 60 100 mV
VIT– Negative-going receiver differential-input voltage threshold –100 –60 mV
VHYS(1) Receiver differential-input voltage threshold hysteresis (VIT+ – VIT– ) 40 120 mV
VOH Receiver high-level output voltage IOH = –8 mA 4 VCC – 0.3 V
VOL Receiver low-level output voltage IOL = 8 mA 0.2 0.4 V
IOZ Receiver high-impedance output current VO = 0 V or VCC, RE = VCC –1 1 µA
IOSR Receiver output short-circuit current RE = 0, DE = 0 See Figure 13 95 mA
Logic
IIN Input current (D, DE, RE) –2 2 µA
Supply
ICC Supply current (quiescent) Driver and receiver enabled DE = VCC, RE = 0, no load 820 1100 µA
Driver enabled, receiver disabled DE = VCC, RE = VCC, no load 520 660
Driver disabled, receiver enabled DE = 0, RE = 0, no load 520 660
Driver and receiver disabled DE = 0, RE = VCC, no load 0.03 1
(1) Under any specific conditions, VIT+ is specified to be at least VHYS higher thanVIT–.