Refer to the PDF data sheet for device specific package drawings
THVD15xx is a family of noise-immune RS-485/RS-422 transceivers designed to operate in rugged industrial environments. The bus pins of these devices are robust to high levels of IEC electrical fast transients (EFT) and IEC electrostatic discharge (ESD) events, eliminating the need for additional system-level protection components.
Each of these devices operates from a single 5-V supply. The devices in this family feature an extended common-mode voltage range which makes them suitable for multi-point applications over long cable runs.
THVD15xx family of devices is available in small VSSOP packages for space-constrained applications. These devices are characterized over ambient free-air temperatures from –40°C to 125°C.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
THVD1510
THVD1550 |
VSSOP (8) | 3.00 mm × 3.00 mm |
SOIC (8) | 4.90 mm × 3.91 mm | |
THVD1551 | VSSOP (8) | 3.00 mm × 3.00 mm |
THVD1512 | VSSOP (10) | 3.00 mm × 3.00 mm |
THVD1552 | VSSOP (10) | 3.00 mm × 3.00 mm |
SOIC (14) | 8.65 mm × 3.91 mm |
Changes from B Revision (July 2018) to C Revision
Changes from A Revision (January 2018) to B Revision
Changes from * Revision (September 2017) to A Revision
PART NUMBER | DUPLEX | ENABLES | SIGNALING RATE | NODES |
---|---|---|---|---|
THVD1512 | Full | DE, RE | up to 500 kbps | 256 |
THVD1510 | Half | DE, RE | ||
THVD1552 | Full | DE, RE | up to 50 Mbps | 196 |
THVD1551 | Full | None | ||
THVD1550 | Half | DE, RE |
PIN | I/O | DESCRIPTION | ||
---|---|---|---|---|
NAME | D | DGK | ||
A | 6 | 6 | Bus input/output | Bus I/O port, A (complementary to B) |
B | 7 | 7 | Bus input/output | Bus I/O port, B (complementary to A) |
D | 4 | 4 | Digital input | Driver data input |
DE | 3 | 3 | Digital input | Driver enable, active high (2 MΩ internal pull-down) |
GND | 5 | 5 | Ground | Device ground |
R | 1 | 1 | Digital output | Receive data output |
VCC | 8 | 8 | Power | 5-V supply |
RE | 2 | 2 | Digital input | Receiver enable, active low (2 MΩ internal pull-up) |
PIN | I/O | DESCRIPTION | ||
---|---|---|---|---|
NAME | DGK | |||
A | 8 | Bus input | Bus input, A (complementary to B) | |
B | 7 | Bus input | Bus input, B (complementary to A) | |
D | 3 | Digital input | Driver data input | |
GND | 4 | Ground | Device ground | |
R | 2 | Digital output | Receive data output | |
VCC | 1 | Power | 5-V supply | |
Y | 5 | Bus output | Bus output, Y (complementary to Z) | |
Z | 6 | Bus output | Bus output, Z (complementary to Y) |
PIN | I/O | DESCRIPTION | ||
---|---|---|---|---|
NAME | D | DGS | ||
A | 12 | 9 | Bus input | Bus input, A (complementary to B) |
B | 11 | 8 | Bus input | Bus input, B (complementary to A) |
D | 5 | 4 | Digital input | Driver data input |
DE | 4 | 3 | Digital input | Driver enable, active high (2 MΩ internal pull-down) |
GND | 6, 7(1) | 5 | Ground | Device ground |
NC | 1, 8 | — | — | Internally not connected |
R | 2 | 1 | Digital output | Receive data output |
VCC | — | 10 | Power | 5-V supply. |
13, 14 | — | Power | 5-V supply. These pins are not connected together internally, so power must be applied to both. | |
Y | 9 | 6 | Bus output | Bus output, Y (Complementary to Z) |
Z | 10 | 7 | Bus output | Bus output, Z (Complementary to Y) |
RE | 3 | 2 | Digital input | Receiver enable, active low (2 MΩ internal pull-up) |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Supply voltage | VCC | –0.5 | 7 | V |
Bus voltage | Range at any bus pin (A, B, Y, or Z) as differential or common-mode with respect to GND | –18 | 18 | V |
Input voltage | Range at any logic pin (D, DE, or RE) | –0.3 | 5.7 | V |
Receiver output current | IO | –24 | 24 | mA |
Storage temperature, Tstg | –65 | 150 | °C |
VALUE | UNIT | ||||
---|---|---|---|---|---|
V(ESD) | Electrostatic discharge | Contact discharge, per IEC 61000-4-2 | Bus terminals and GND | ±18,000 | V |
Air-gap discharge, per IEC 61000-4-2 | Bus terminals and GND | ±25,000 | |||
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | Bus terminals and GND | ±30,000 | |||
All pins except Bus terminals and GND | ±8,000 | ||||
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1,500 | ||||
Machine model (MM), per JEDEC JESD22-A115-A | ±200 | ||||
V(EFT) | Electrical fast transient | Per IEC 61000-4-4 | Bus terminals | ±4,000 | V |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
VCC | Supply voltage | 4.5 | 5.5 | V | ||
VI | Input voltage at any bus terminal(1) | -15 | 15 | V | ||
VIH | High-level input voltage (driver, driver enable, and receiver enable inputs) | 2 | VCC | V | ||
VIL | Low-level input voltage (driver, driver enable, and receiver enable inputs) | 0 | 0.8 | V | ||
VID | Differential input voltage | -15 | 15 | V | ||
IO | Output current, driver | -60 | 60 | mA | ||
IOR | Output current, receiver | -8 | 8 | mA | ||
RL | Differential load resistance | 54 | Ω | |||
1/tUI | Signaling rate | THVD1510, THVD1512 | 500 | kbps | ||
THVD1550, THVD1551, THVD1552 | 50 | Mbps | ||||
TA | Operating ambient temperature | -40 | 125 | °C | ||
TJ | Junction temperature | -40 | 150 | °C |
THERMAL METRIC(1) | THVD1510
THVD1550 |
THVD1552 | THVD1510
THVD1550 THVD1551 |
THVD1512
THVD1552 |
UNIT | |
---|---|---|---|---|---|---|
D (SOIC) | D (SOIC) | DGK (VSSOP) | DGS (VSSOP) | |||
8 PINS | 14 PINS | 8 PINS | 10 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 112.4 | 88.0 | 151.7 | 151.4 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 62.7 | 45.4 | 62.8 | 59.3 | °C/W |
RθJB | Junction-to-board thermal resistance | 62.0 | 44.1 | 81.3 | 81.6 | °C/W |
ψJT | Junction-to-top characterization parameter | 15.4 | 11.3 | 7.8 | 6.5 | °C/W |
ψJB | Junction-to-board characterization parameter | 61.3 | 43.7 | 79.8 | 79.9 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | N/A | N/A | N/A | N/A | °C/W |
PARAMETER | TEST CONDITIONS | VALUE | UNIT | |||
---|---|---|---|---|---|---|
PD | Driver and receiver enabled,
VCC = 5.5 V, TA = 125 °C, 50% duty cycle square wave at signaling rate |
Unterminated
RL = 300 Ω, CL = 50 pF (driver) |
THVD151x | 500 kbps | 210 | mW |
THVD155x | 50 Mbps | 350 | ||||
RS-422 load
RL = 100 Ω, CL = 50 pF (driver) |
THVD151x | 500 kbps | 220 | mW | ||
THVD155x | 50 Mbps | 330 | ||||
RS-485 load
RL = 54 Ω, CL = 50 pF (driver) |
THVD151x | 500 kbps | 250 | mW | ||
THVD155x | 50 Mbps | 340 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|---|---|
Driver | ||||||||
|VOD| | Driver differential output voltage magnitude | RL = 60 Ω, -15 V ≤ Vtest ≤ 15 V, (See Figure 11) | 1.5 | 2.7 | V | |||
RL = 100 Ω (See Figure 12) | 2 | 3 | V | |||||
RL = 54 Ω (See Figure 12) | 1.5 | 2.7 | V | |||||
Δ|VOD| | Change in differential output voltage | RL = 54 Ω (See Figure 12) | –200 | 200 | mV | |||
VOC | Common-mode output voltage | 1 | VCC/2 | 3 | V | |||
ΔVOC(SS) | Change in steady-state common-mode output voltage | –200 | 200 | mV | ||||
IOS | Short-circuit output current | DE = VCC, -15 V ≤ VO ≤ 15V | –250 | 250 | mA | |||
Receiver | ||||||||
II | Bus input current | DE = 0 V, VCC = 0 V or 5.5 V | THVD151x | VI = 12 V | 75 | 125 | μA | |
VI = 15 V | 95 | 156 | ||||||
VI = -7 V | -100 | -40 | ||||||
VI = -15 V | -215 | -85 | ||||||
THVD155x | VI = 12 V | 115 | 160 | |||||
VI = 15 V | 150 | 200 | ||||||
VI = -7 V | -130 | -75 | ||||||
VI = -15 V | -280 | -180 | ||||||
Receiver | ||||||||
VTH+ | Positive-going input threshold voltage | Over common-mode range of - 7 V to +12 V | See(1) | –85 | –20 | mV | ||
VTH- | Negative-going input threshold voltage | –200 | –135 | See(1) | mV | |||
VHYS | Input hysteresis | 50 | mV | |||||
VTH+ | Positive-going input threshold voltage | Over common-mode range of ± 15 V | See(1) | –85 | –20 | mV | ||
VTH- | Negative-going input threshold voltage | –220 | –135 | See(1) | mV | |||
VHYS | Input hysteresis | 50 | mV | |||||
VOH | Output high voltage | IOH = -8 mA | 4 | VCC - 0.3 | V | |||
VOL | Output low voltage | IOL = 8 mA | 0.2 | 0.4 | V | |||
IOZ | Output high-impedance current | VO = 0 V or VCC, RE = VCC | -1 | 1 | µA | |||
Logic | ||||||||
IIN | Input current (D, DE, RE) | 4.5 V ≤ VCC ≤ 5.5 V, 0 V ≤ VIN ≤ VCC | –5 | 0 | 5 | µA | ||
Supply | ||||||||
ICC | Supply current (quiescent) | Driver and receiver enabled | RE = 0 V, DE = VCC, No load | 700 | 1000 | µA | ||
Driver enabled, receiver disabled | RE = VCC, DE = VCC, No load | 400 | 620 | µA | ||||
Driver disabled, receiver enabled | RE = 0 V, DE = 0 V, No load | 400 | 630 | µA | ||||
Driver and receiver disabled | RE = VCC, DE = 0 V, D = open, No load | 0.1 | 1 | µA | ||||
TSD | Thermal shutdown temperature | 170 | °C |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
Driver | |||||||
tr, tf | Differential output rise/fall time | RL = 54 Ω, CL = 50 pF | See Figure 13 | 300 | 400 | 600 | ns |
tPHL, tPLH | Propagation delay | 350 | 500 | ns | |||
tSK(P) | Pulse skew, |tPHL – tPLH| | 15 | ns | ||||
tPHZ, tPLZ | Disable time (THVD1510, THVD1512) | See Figure 14 and Figure 15 | 110 | 200 | ns | ||
tPZH, tPZL | Enable time (THVD1510, THVD1512) | RE = 0 V | 100 | 500 | ns | ||
RE = VCC | 2 | 4 | µs | ||||
Receiver | |||||||
tr, tf | Differential output rise/fall time | CL = 15 pF | See Figure 16 | 15 | 25 | ns | |
tPHL, tPLH | Propagation delay | 50 | 60 | ns | |||
tSK(P) | Pulse skew, |tPHL – tPLH| | 10 | ns | ||||
tPHZ, tPLZ | Disable time (THVD1510, THVD1512) | 30 | 40 | ns | |||
tPZH(1),
tPZL(1), tPZH(2), tPZL(2) |
Enable time (THVD1510, THVD1512) | DE = VCC | See Figure 17 | 60 | 100 | ns | |
DE = 0 V | See Figure 18 | 3 | 8 | μs |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
Driver | |||||||
tr, tf | Differential output rise/fall time | RL = 54 Ω, CL = 50 pF | See Figure 13 | 1 | 2 | 6 | ns |
tPHL, tPLH | Propagation delay | 5 | 10 | 16 | ns | ||
tSK(P) | Pulse skew, |tPHL – tPLH| | 3.5 | ns | ||||
tPHZ, tPLZ | Disable time (THVD1550, THVD1552) | See Figure 14 and Figure 15 | 10 | 22 | ns | ||
tPZH, tPZL | Enable time (THVD1550, THVD1552) | RE = 0 V | 10 | 22 | ns | ||
RE = VCC | 2 | 4 | μs | ||||
Receiver | |||||||
tr, tf | Differential output rise/fall time | CL = 15 pF | See Figure 16 | 1 | 3 | 6 | ns |
tPHL, tPLH | Propagation delay | 30 | 45 | ns | |||
tSK(P) | Pulse skew, |tPHL – tPLH| | 2 | ns | ||||
tPHZ, tPLZ | Disable time (THVD1550, THVD1552) | 8 | 18 | ns | |||
tPZH(1),
tPZL(1), tPZH(2), tPZL(2) |
Enable time (THVD1550, THVD1552) | DE = VCC | See Figure 17 | 55 | 90 | ns | |
DE = 0 V | See Figure 18 | 3 | 8 | μs |
VCC = 5 V | DE = VCC | D = 0 V |
TA = 25°C | RL = 54 Ω | D = VCC |
DE = VCC |
RL = 54 Ω |
VCC = 5 V | DE = VCC | D = 0 V |
RL = 54 Ω |
THVD1510 and THVD1550 are low-power, half-duplex RS-485 transceivers available in two speed grades suitable for data transmission up to 500 kbps and 50 Mbps respectively.
THVD1551 is fully enabled with no external enabling pins. THVD1512 and THVD1552 have active-high driver enables and active-low receiver enables. A standby current of less than 1 µA can be achieved by disabling both driver and receiver.
Internal ESD protection circuits of the THVD15xx protect the transceivers against electrostatic discharges (ESD) according to IEC 61000-4-2 of up to ±18 kV and against electrical fast transients (EFT) according to IEC 61000-4-4 of up to ±4 kV. With careful system design, one could achieve ±4 kV EFT Criterion A (no data loss when transient noise is present).
The THVD15xx device family provides internal biasing of the receiver input thresholds in combination with large input-threshold hysteresis. The receiver output remains logic high under a bus-idle or bus-short conditions without the need for external failsafe biasing resistors. Device operation is specified over a wide ambient temperature range from –40°C to 125°C.
When the driver enable pin, DE, is logic high, the differential outputs A and B follow the logic states at data input D. A logic high at D causes A to turn high and B to turn low. In this case the differential output voltage defined as VOD = VA – VB is positive. When D is low, the output states reverse: B turns high, A becomes low, and VOD is negative.
When DE is low, both outputs turn high-impedance. In this condition the logic state at D is irrelevant. The DE pin has an internal pull-down resistor to ground, thus when left open the driver is disabled (high-impedance) by default. The D pin has an internal pull-up resistor to VCC, thus, when left open while the driver is enabled, output A turns high and B turns low.
INPUT | ENABLE | OUTPUTS | FUNCTION | |
---|---|---|---|---|
D | DE | A | B | |
H | H | H | L | Actively drive bus high |
L | H | L | H | Actively drive bus low |
X | L | Z | Z | Driver disabled |
X | OPEN | Z | Z | Driver disabled by default |
OPEN | H | H | L | Actively drive bus high by default |
When the receiver enable pin, RE, is logic low, the receiver is enabled. When the differential input voltage defined as VID = VA – VB is higher than the positive input threshold, VTH+, the receiver output, R, turns high. When VID is lower than the negative input threshold, VTH-, the receiver output, R, turns low. If VID is between VTH+ and VTH- the output is indeterminate.
When RE is logic high or left open, the receiver output is high-impedance and the magnitude and polarity of VID are irrelevant. Internal biasing of the receiver inputs causes the output to go failsafe-high when the transceiver is disconnected from the bus (open-circuit), the bus lines are shorted to one another (short-circuit), or the bus is not actively driven (idle bus).
DIFFERENTIAL INPUT | ENABLE | OUTPUT | FUNCTION |
---|---|---|---|
VID = VA – VB | RE | R | |
VTH+ < VID | L | H | Receive valid bus high |
VTH- < VID < VTH+ | L | ? | Indeterminate bus state |
VID < VTH- | L | L | Receive valid bus low |
X | H | Z | Receiver disabled |
X | OPEN | Z | Receiver disabled by default |
Open-circuit bus | L | H | Fail-safe high output |
Short-circuit bus | L | H | Fail-safe high output |
Idle (terminated) bus | L | H | Fail-safe high output |
For this device, the driver and receiver are fully enabled, thus the differential outputs Y and Z follow the logic states at data input D at all times. A logic high at D causes Y to turn high and Z to turn low. In this case, the differential output voltage defined as VOD = VY – VZ is positive. When D is low, the output states reverse: Z turns high, Y becomes low, and VOD is negative. The D pin has an internal pull-up resistor to VCC, thus, when left open while the driver is enabled, output Y turns high and Z turns low.
INPUT | OUTPUTS | FUNCTIONS | |
---|---|---|---|
D | Y | Z | |
H | H | L | Actively drive bus high |
L | L | H | Actively drive bus low |
OPEN | H | L | Actively drive bus high by default |
When the differential input voltage defined as VID = VA – VB is higher than the positive input threshold, VTH+, the receiver output, R, turns high. When VID is less than the negative input threshold, VTH–, the receiver output, R, turns low. If VID is between VTH+ and VTH– the output is indeterminate. Internal biasing of the receiver inputs causes the output to go failsafe-high when the transceiver is disconnected from the bus (open-circuit), the bus lines are shorted to one another (short-circuit), or the bus is not actively driven (idle bus).
DIFFERENTIAL INPUT | OUTPUT | FUNCTION |
---|---|---|
VID = VA – VB | R | |
VTH+ < VID | H | Receive valid bus high |
VTH- < VID < VTH+ | ? | Indeterminate bus state |
VID < VTH- | L | Receive valid bus low |
Open-circuit bus | H | Fail-safe high output |
Short-circuit bus | H | Fail-safe high output |
Idle (terminated) bus | H | Fail-safe high output |
When the driver enable pin, DE, is logic high, the differential outputs Y and Z follow the logic states at data input D. A logic high at D causes Y to turn high and Z to turn low. In this case the differential output voltage defined as VOD = VY – VZ is positive. When D is low, the output states reverse: Z turns high, Y becomes low, and VOD is negative.
When DE is low, both outputs turn high-impedance. In this condition the logic state at D is irrelevant. The DE pin has an internal pull-down resistor to ground, thus when left open the driver is disabled (high-impedance) by default. The D pin has an internal pull-up resistor to VCC, thus, when left open while the driver is enabled, output Y turns high and Z turns low.
INPUT | ENABLE | OUTPUTS | FUNCTION | |
---|---|---|---|---|
D | DE | Y | Z | |
H | H | H | L | Actively drive bus high |
L | H | L | H | Actively drive bus low |
X | L | Z | Z | Driver disabled |
X | OPEN | Z | Z | Driver disabled by default |
OPEN | H | H | L | Actively drive bus high by default |
When the receiver enable pin, RE, is logic low, the receiver is enabled. When the differential input voltage defined as VID = VA – VB is higher than the positive input threshold, VTH+, the receiver output, R, turns high. When VID is lower than the negative input threshold, VTH-, the receiver output, R, turns low. If VID is between VTH+ and VTH- the output is indeterminate.
When RE is logic high or left open, the receiver output is high-impedance and the magnitude and polarity of VID are irrelevant. Internal biasing of the receiver inputs causes the output to go failsafe-high when the transceiver is disconnected from the bus (open-circuit), the bus lines are shorted to one another (short-circuit), or the bus is not actively driven (idle bus).
DIFFERENTIAL INPUT | ENABLE | OUTPUT | FUNCTION |
---|---|---|---|
VID = VA – VB | RE | R | |
VTH+ < VID | L | H | Receive valid bus high |
VTH- < VID < VTH+ | L | ? | Indeterminate bus state |
VID < VTH- | L | L | Receive valid bus low |
X | H | Z | Receiver disabled |
X | OPEN | Z | Receiver disabled by default |
Open-circuit bus | L | H | Fail-safe high output |
Short-circuit bus | L | H | Fail-safe high output |
Idle (terminated) bus | L | H | Fail-safe high output |
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The THVD15xx family consists of half-duplex and full-duplex RS-485 transceivers commonly used for asynchronous data transmissions. For half-duplex devices, the driver and receiver enable pins allow for the configuration of different operating modes. Full-duplex implementation requires two signal pairs (four wires), and allows each node to transmit data on one pair while simultaneously receiving data on the other pair.
An RS-485 bus consists of multiple transceivers connecting in parallel to a bus cable. To eliminate line reflections, each cable end is terminated with a termination resistor, RT, whose value matches the characteristic impedance, Z0, of the cable. This method, known as parallel termination, generally allows for higher data rates over longer cable length.
RS-485 is a robust electrical standard suitable for long-distance networking that may be used in a wide range of applications with varying requirements, such as distance, data rate, and number of nodes.
There is an inverse relationship between data rate and cable length, which means the higher the data rate, the shorter the cable length; and conversely, the lower the data rate, the longer the cable length. While most RS-485 systems use data rates between 10 kbps and 100 kbps, some applications require data rates up to 250 kbps at distances of 4000 feet and longer. Longer distances are possible by allowing for small signal jitter of up to 5 or 10%.
Even higher data rates are achievable (that is, 50 Mbps for the THVD1550, THVD1551 and THVD1552) in cases where the interconnect is short enough (or has suitably low attenuation at signal frequencies) to not degrade the data.