SLLSFQ9B May 2024 – October 2024 THVD2410V-EP , THVD2450V-EP , THVD2452V-EP
PRODUCTION DATA
NAME | PIN NO. | TYPE | DESCRIPTION | |
---|---|---|---|---|
DRC | D | |||
VIO | 1 | 1 | Logic Supply | 1.65V to 5.5V supply for logic I/O signals R, RE, D, DE, and SLR) |
R | 2 | 2 | Digital Output | Receive data output |
DE | 3 | 4 | Digital Input | Driver enable input; integrated pull-down |
RE | 4 | 3 | Digital Input | Receiver enable input; integrated pull-up |
D | 5 | 5 | Digital Input | Transmission data input; integrated pull-up |
GND | 6 | 6 | Reference Potential | Local device ground |
SLR | 7 | 8 | Digital Input | Slew rate select ; integrated pull-down. For THVD2410V-EP: Low = 1Mbps, High = 250kbps. Defaults to 1Mbps if SLR is left floating. For THVD2450V-EP and THVD2452V-EP: Low = 50Mbps, High = 20Mbps. Defaults to 50Mbps if left floating. |
A | 8 | 12 | Bus Input | Bus I/O (half-duplex), bus input (full-duplex) |
B | 9 | 11 | Bus Input | Bus I/O (half-duplex), bus input (full-duplex) |
VCC | 10 | 14 | Bus Supply | 3V to 5.5V supply for the transceiver |
Y | - | 9 | Bus Output | Bus output, Y |
Z | - | 10 | Bus Output | Bus output, Z |
NC | - | 7, 13 | No connect pin. Internally not connected |