SLLSFD6A May   2020  – March 2021 THVD8000

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 ESD Ratings - IEC Specifications
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Power Dissipation Characteristics
    8. 6.8 Switching Characteristics
    9. 6.9 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 OOK Modulation with F_SET pin
      2. 8.3.2 OOK Demodulation
      3. 8.3.3 Transmitter Timeout
      4. 8.3.4 Polarity Free Operation
      5. 8.3.5 Glitch Free Mode Change
      6. 8.3.6 Integrated IEC ESD and EFT Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 OOK Mode
      2. 8.4.2 Thermal shutdown (TSD)
  9. Application Information Disclaimer
    1. 9.1 Application information
    2. 9.2 Typical application (OOK mode)
      1. 9.2.1 Design requirements
        1. 9.2.1.1 Carrier frequency
      2. 9.2.2 Detailed design procedure
        1. 9.2.2.1 Inductor value selection
        2. 9.2.2.2 Capacitor value selection
      3. 9.2.3 Application Curves
  10. 10Power supply recommendations
  11. 11Layout
    1. 11.1 Layout guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Layout guidelines

Robust and reliable bus node design often requires the use of external transient protection devices in order to protect against surge transients that may occur in industrial environments. Since these transients have a wide frequency bandwidth (from approximately 3 MHz to 300 MHz), high-frequency layout techniques should be applied during PCB design.

  1. Place the protection circuitry close to the bus connector to prevent noise transients from propagating across the board.
  2. Use VCC and ground planes to provide low inductance. Note that high-frequency currents tend to follow the path of least impedance and not the path of least resistance.
  3. Place F_SET components near the pin to keep capacitance load below recommended value
  4. Use a pull up or down resistor on mode to set a default state
  5. Apply 100-nF to 220-nF decoupling capacitors as close as possible to the VCC pins of transceiver, UART and/or controller ICs on the board.
  6. Use at least two vias for VCC and ground connections of decoupling capacitors and protection devices to minimize effective via inductance.
  7. Use 1-kΩ to 10-kΩ pull-up and pull-down resistors for enable lines to limit noise currents in theses lines during transient events.
  8. Insert pulse-proof resistors into the A and B bus lines if the TVS clamping voltage is higher than the specified maximum voltage of the transceiver bus pins. These resistors limit the residual clamping current into the transceiver and prevent it from latching up.
  9. While pure TVS protection is sufficient for surge transients up to 1 kV, higher transients require metal-oxide varistors (MOVs) which reduce the transients to a few hundred volts of clamping voltage, and transient blocking units (TBUs) that limit transient current to less than 1 mA.