SLLSFQ8 January   2024 THVD9491-SEP

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 ESD Ratings [IEC]
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Thermal Information
    6. 5.6 Power Dissipation
    7. 5.7 Electrical Characteristics
    8. 5.8 Switching Characteristics: 20Mbps
    9. 5.9 Switching Characteristics: 50Mbps
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 ±70-V Fault Protection
      2. 7.3.2 Integrated IEC ESD and EFT Protection
      3. 7.3.3 Driver Overvoltage and Overcurrent Protection
      4. 7.3.4 Enhanced Receiver Noise Immunity
      5. 7.3.5 Receiver Fail-Safe Operation
      6. 7.3.6 Low-Power Shutdown Mode
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Data Rate and Bus Length
        2. 8.2.1.2 Stub Length
        3. 8.2.1.3 Bus Loading
        4. 8.2.1.4 Transient Protection
      2. 8.2.2 Detailed Design Procedure
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information
    2. 11.2 Mechanical Data

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

THVD9491-SEP is a space enhanced, ±70V fault-protected full-duplex RS-422/RS-485 transceiver using a 1.65V to 5.5V logic supply for data and enable logic signals, and a 3V to 5.5V bus side supply. The device has a slew rate select feature that enables the use at two maximum speeds based on the SLR pin setting.

The device features integrated IEC ESD protection, eliminating the need for external system-level protection components. The ±12V input common-mode range makes reliable data communication over longer cable run lengths and/or in the presence of large ground loop voltages. Enhanced 250mV receiver hysteresis provides high noise rejection. In addition, the receiver fail-safe feature makes sure of a logic high when the inputs are open or shorted together.

THVD9491-SEP device is available in a standard
14-pin SOIC package.

Package Information
PART NUMBERPACKAGE(1)PACKAGE SIZE(2)
THVD9491-SEPSOIC (D, 14)8.65mm × 6mm
(1) For more information, see Section 11.
(2) The package size (length × width) is a nominal value and includes pins, where applicable.
GUID-20220305-SS0I-DGJP-2NVN-V2XQQHLZVWQL-low.svgSimplified Schematic