SLLSFQ8 January   2024 THVD9491-SEP

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 ESD Ratings [IEC]
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Thermal Information
    6. 5.6 Power Dissipation
    7. 5.7 Electrical Characteristics
    8. 5.8 Switching Characteristics: 20Mbps
    9. 5.9 Switching Characteristics: 50Mbps
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 ±70-V Fault Protection
      2. 7.3.2 Integrated IEC ESD and EFT Protection
      3. 7.3.3 Driver Overvoltage and Overcurrent Protection
      4. 7.3.4 Enhanced Receiver Noise Immunity
      5. 7.3.5 Receiver Fail-Safe Operation
      6. 7.3.6 Low-Power Shutdown Mode
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Data Rate and Bus Length
        2. 8.2.1.2 Stub Length
        3. 8.2.1.3 Bus Loading
        4. 8.2.1.4 Transient Protection
      2. 8.2.2 Detailed Design Procedure
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information
    2. 11.2 Mechanical Data

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Meets or exceeds the requirements of the TIA/EIA-485A and TIA/EIA-422B standards
  • Total ionizing dose (TID) characterized up to 30krad (Si)
    • Total ionizing dose radiation lot acceptance testing (TID RLAT) for every wafer lot to 30krad (Si)
  • Single-event effects (SEE) characterized
    • Single event latch-up (SEL) immune to linear energy transfer (LET) = 43MeV⋅cm2 /mg at 125°C
  • Space enhanced plastic (Space EP)
    • Controlled baseline
    • One assembly and test site
    • One fabrication site
    • Gold bond wire
    • NiPdAu lead finish
    • Military temp range (-55°C to 125°C)
    • Extended product life cycle
    • Product traceability
    • Meets the NASA ASTM E595 outgassing specification
  • 3V to 5.5V supply voltage
  • 1.65V to 5.5V Supply for data and enable signals
  • SLR Pin Selectable Data Rates:
    • 20Mbps and 50Mbps
  • Bus I/O protection
    • ±70V DC bus fault
    • ±16kV HBM ESD
    • ±8kV IEC 61000-4-2 contact discharge
    • ±4kV IEC 61000-4-4 fast transient burst
  • Symmetric common mode range: ±12V
  • Enhanced receiver hysteresis for noise immunity
  • Glitch-free power-up or down for hot plug-in capability
  • Open, short, and idle bus failsafe
  • 1/8 unit load (up to 256 bus nodes)
  • Leaded 14-pin SOIC package