SCPS268A September   2017  – February 2022 TIC10024-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VS Pin
      2. 8.3.2  VDD Pin
      3. 8.3.3  Device Initialization
      4. 8.3.4  Device Trigger
      5. 8.3.5  Device Reset
        1. 8.3.5.1 VS Supply POR
        2. 8.3.5.2 Hardware Reset
        3. 8.3.5.3 Software Reset
      6. 8.3.6  VS Under-Voltage (UV) Condition
      7. 8.3.7  VS Over-Voltage (OV) Condition
      8. 8.3.8  Switch Inputs Settings
        1. 8.3.8.1 Input Current Source and Sink Selection
        2. 8.3.8.2 Input Enable Selection
        3. 8.3.8.3 Thresholds Adjustment
        4. 8.3.8.4 Wetting Current Configuration
      9. 8.3.9  Interrupt Generation and INT Assertion
        1. 8.3.9.1 INT Pin Assertion Scheme
        2. 8.3.9.2 Interrupt Idle Time (tINT_IDLE) Time
        3. 8.3.9.3 Microcontroller Wake-Up
        4. 8.3.9.4 Interrupt Enable / Disable And Interrupt Generation Conditions
        5. 8.3.9.5 Detection Filter
      10. 8.3.10 Temperature Monitor
        1. 8.3.10.1 Temperature Warning (TW)
        2. 8.3.10.2 Temperature Shutdown (TSD)
      11. 8.3.11 Parity Check And Parity Generation
      12. 8.3.12 Cyclic Redundancy Check (CRC)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Continuous Mode
      2. 8.4.2 Polling Mode
      3. 8.4.3 Additional Features
        1. 8.4.3.1 Clean Current Polling (CCP)
        2. 8.4.3.2 Wetting Current Auto-Scaling
  9. 9 Programming
    1. 9.1 SPI Communication Interface Buses
      1. 9.1.1 Chip Select ( CS)
      2. 9.1.2 System Clock (SCLK)
      3. 9.1.3 Slave In (SI)
      4. 9.1.4 Slave Out (SO)
    2. 9.2 SPI Sequence
      1. 9.2.1 Read Operation
      2. 9.2.2 Write Operation
      3. 9.2.3 Status Flag
    3. 9.3 Programming Guidelines
    4. 9.4 Register Maps
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Digital Switch Detection in Automotive Body Control Module
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Systems Examples
      1. 10.3.1 Using TIC10024-Q1 in a 12 V Automotive System
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Receiving Notification of Documentation Updates
    2. 13.2 Community Resources
    3. 13.3 Trademarks
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.6 VS Under-Voltage (UV) Condition

During normal operation of a typical 12 V automotive system, the VS voltage is usually quite stable and stays well above 11 V. However, the VS voltage may drop temporarily during certain vehicle operations, such as cold cranking. If the VS voltage drops below VUV_F, the TIC10024-Q1 enters the under-voltage (UV) condition since there is not enough voltage headroom for the device to accurately generate wetting currents. The following describes the behavior of the TIC10024-Q1 under UV condition:

  1. All current sources and sinks de-activate and switch monitoring stops.
  2. Interrupt is generated by asserting the INT pin low and the bit UV in the interrupt register (INT_STAT) is flagged to logic 1. The bit UV_STAT is asserted to logic 1 in the register IN_STAT_MISC. The OI SPI flag is asserted during any SPI transactions. The INT pin is released and the interrupt register (INT_STAT) is cleared on the rising edge of CS provided that the interrupt register has been read during the SPI transaction.
  3. SPI communication stays active, and all register settings stay intact without resetting. Previous switch status, if needed, can be retrieved without interruption.
  4. The device continues to monitor the VS voltage, and the UV condition sustains if the VS voltage continues to stay below VUV_R. No further interrupt is generated once cleared.

Note the device resets as described in section VS Supply POR if the VS voltage drops below VPOR_F.

When the VS voltage rises above VUV_R, the INT pin is asserted low to notify the microcontroller that the UV condition no longer exists. The UV bit in the register INT_STAT is flagged to logic 1 and the bit UV_STAT bit is de-asserted to logic 0 in the register IN_STAT_MISC to reflect the clearance of the UV condition. The device resumes operation using current register settings (regardless of the INT pin and SPI communication status) with polling restarted from the first enabled channel. The Switch State Change (SSC) interrupt is generated at the end of the first polling cycle and the detected switch status becomes the baseline switch status for subsequent polling cycles. The content of the INT_STAT register, once read by the microcontroller, is cleared, and the INT pin is released afterwards.

The following diagram describes the TIC10024-Q1 operation at various different VS voltages. If the VS voltage stays above VUV_F (Case 1), the device stays in normal operation. If the VS voltage drops below VUV_F but stays above VPOR_F (Case 2), the device enters the UV condition. If VS voltage drops below VPOR_F (Case 3), the device resets and all register settings are cleared. The microcontroller is then required to re-program all the configuration registers in order to resume normal operation after the VS voltage recovers.

GUID-B1F50611-7C4B-4B15-AFC5-6B018D13BA6A-low.gifFigure 8-2 TIC10024-Q1 Operation At Various VS Voltage Levels