SCPS260 Data sheet

SCPS260C August 2017 – February 2022 TIC12400-Q1

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

DCP|38
- MPDS520B

Thermal pad, mechanical data (Package|Pins)

DCP|38
- PPTD170A

Orderable Information

8.6 Register Maps

Table 8-11 lists the memory-mapped registers for the TIC12400-Q1. All register offset addresses not listed in Table 8-11 should be considered as reserved locations and the register contents should not be modified.

Table 8-11 TIC12400-Q1 Registers

OFFSET	TYPE	RESET	ACRONYM	REGISTER NAME	SECTION
1h	R	20h	DEVICE_ID	Device ID Register	Go
2h	RC	1h	INT_STAT	Interrupt Status Register	Go
3h	R	FFFFh	CRC	CRC Result Register	Go
4h	R	0h	IN_STAT_MISC	Miscellaneous Status Register	Go
5h	R	0h	IN_STAT_COMP	Comparator Status Register	Go
6h-7h	R	0h	IN_STAT_ADC0, IN_STAT_ADC1	ADC Status Register	Go
8h-9h	R	0h	IN_STAT_MATRIX0, IN_STAT_MATRIX1	Matrix Status Register	Go
Ah-16h	R	0h	ANA_STAT0- ANA_STAT12	ADC Raw Code Register	Go
17h-19h	—	—	RESERVED	RESERVED	—
1Ah	R/W	0h	CONFIG	Device Global Configuration Register	Go
1Bh	R/W	0h	IN_EN	Input Enable Register	Go
1Ch	R/W	0h	CS_SELECT	Current Source/Sink Selection Register	Go
1Dh-1Eh	R/W	0h	WC_CFG0, WC_CFG1	Wetting Current Configuration Register	Go
1Fh-20h	R/W	0h	CCP_CFG0, CCP_CFG1	Clean Current Polling Register	Go
21h	R/W	0h	THRES_COMP	Comparator Threshold Control Register	Go
22h-23h	R/W	0h	INT_EN_COMP1, INT_EN_COMP2	Comparator Input Interrupt Generation Control Register	Go
24h	R/W	0h	INT_EN_CFG0	Global Interrupt Generation Control Register	Go
25h-28h	R/W	0h	INT_EN_CFG1- INT_EN_CFG4	ADC Input Interrupt Generation Control Register	Go
29h-2Dh	R/W	0h	THRES_CFG0- THRES_CFG4	ADC Threshold Control Register	Go
2Eh- 30h	R/W	0h	THRESMAP_CFG0- THRESMAP_CFG2	ADC Threshold Mapping Register	Go
31h	R/W	0h	Matrix	Matrix Setting Register	Go
32h	R/W	0h	Mode	Mode Setting Register	Go

8.6.1 DEVICE_ID Register (Offset = 1h) [Reset = 20h]

DEVICE_ID is shown in Figure 8-24 and described in Table 8-12.

Return to Summary Table.

This register represents the device ID of the TIC12400-Q1.

Figure 8-24 DEVICE_ID Register

23	22	21	20	19	18	17	16	15	14	13	12
RESERVED
R-0h

11	10	9	8	7	6	5	4	3	2	1	0
RESERVED	MAJOR							MINOR
R-0h	R-2h							R-0h

LEGEND: R = Read only

Table 8-12 DEVICE_ID Register Field Descriptions

Bit	Field	Type	Reset	Description
23-11	RESERVED	R	0h	RESERVED
10-4	MAJOR	R	2h	These 7 bits represents major revision ID. For TIC12400-Q1 the major revision ID is 2h.
3-0	MINOR	R	0h	These 4 bits represents minor revision ID. For TIC12400-Q1 the minor revision ID is 0h

8.6.2 INT_STAT Register (Offset = 2h) [reset = 1h]

INT_STAT is shown in Figure 8-25 and described in Table 8-13.

Return to Summary Table.

This register records the information of the event as it occurs in the device. A READ command executed on this register clears its content and resets the register to its default value. The INT pin is released at the rising edge of the CS pin from the READ command.

Figure 8-25 INT_STAT Register

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED		CHK_FAIL	ADC_DIAG	WET_DIAG	VS1	VS0	CRC_CALC
R-0h		RC-0h	RC-0h	RC-0h	RC-0h	RC-0h	RC-0h

7	6	5	4	3	2	1	0
UV	OV	TW	TSD	SSC	PRTY_FAIL	SPI_FAIL	POR
RC-0h	RC-0h	RC-0h	RC-0h	RC-0h	RC-0h	RC-0h	RC-1h

LEGEND: R = Read only; RC = Read to clear

Table 8-13 INT_STAT Register Field Descriptions

Bit	Field	Type	Reset	Description
23-14	RESERVED	R	0h	RESERVED
13	CHK_FAIL	RC	0h	0h = Default factory setting is successfully loaded upon device initialization or the event status got cleared after a READ command was executed on the INT_STAT register. 1h = An error is detected when loading factory settings into the device upon device initialization. During device initialization, factory settings are programmed into the device to allow proper device operation. The device performs a self-check after the device is programmed to diagnose whether correct settings are loaded. If the self-check returns an error, the CHK_FAIL bit is flagged to logic 1 along with the POR bit. The host controller is then recommended to initiate a software reset (see section Software Reset) to re-initialize the device and allow correct settings to be re-programmed.
12	ADC_DIAG	RC	0h	0h = No ADC self-diagnostic error is detected or the event status got cleared after a READ command was executed on the INT_STAT register. 1h = ADC self-diagnostic error is detected. The ADC Self-Diagnostic feature (see section ADC Self-Diagnostic) can be activated to monitor the integrity of the internal ADC. The ADC_DIAG bit is flagged to logic 1 if an ADC error is diagnosed.
11	WET_DIAG	RC	0h	0h = No wetting current error is detected, or the event status got cleared after a READ command was executed on the INT_STAT register. 1h = Wetting current error is detected. The Wetting Current Diagnostic feature (see section Wetting Current Diagnostic) can be activated to monitor the integrity of the internal current sources or sinks. The WET_DIAG bit is flagged to logic 1 if a wetting current error is diagnosed.
10	VS1	RC	0h	0h = No V_S voltage state change occurred with respect to VS1_THRES2A or VS1_THRES2B or the status got cleared after a READ command was executed on the INT_STAT register. 1h = V_S voltage state change occurred with respect to VS1_THRES2A or VS1_THRES2B. The VS1 interrupt bit indicates whether V_S voltage state change occurred with respect to thresholds VS1_THRES2A and VS1_THRES2B if the V_S Measurement feature (see section VS Measurement) is activated.
9	VS0	RC	0h	0h = No V_S voltage state change occurred with respect to VS0_THRES2A or VS0_THRES2B or the status got cleared after a READ command was executed on the INT_STAT register. 1h = V_S voltage state change occurred with respect to VS0_THRES2A or VS0_THRES2B. The VS0 interrupt bit indicates whether V_S voltage state change occurred with respect to thresholds VS0_THRES2A and VS0_THRES2B if the V_S Measurement feature (see section VS Measurement) is activated.
8	CRC_CALC	RC	0h	0h = CRC calculation is running, not started, or was acknowledged after a READ command was executed on the INT_STAT register. 1h = CRC calculation is finished. CRC calculation (see section Cyclic Redundancy Check (CRC)) can be triggered to make sure correct register values are programmed into the device. Once the calculation is completed, the CRC_CALC bit is flagged to logic 1 to indicate completion of the calculation, and the result can then be accessed from the CRC (offset = 3h) register.
7	UV	RC	0h	0h = No under-voltage condition occurred or cleared on the V_S pin, or the event status got cleared after a READ command was executed on the INT_STAT register. 1h = Under-voltage condition occurred or cleared on the V_S pin. When the UV bit is flagged to logic 1, it indicates the Under-Voltage (UV) event has occurred. The bit is also flagged to logic 1 when the event clears. For more details about the UV operation, please refer to section VS under-voltage (UV) condition.
6	OV	RC	0h	0h = No over-voltage condition occurred or cleared on the V_S pin, or the event status got cleared after a READ command was executed on the INT_STAT register. 1h = Over-voltage condition occurred or cleared on the V_S pin. When the OV bit is flagged to logic 1, it indicates the Over-Voltage (OV) event has occurred. The bit is also flagged to logic 1 when the event clears. For more details about the OV operation, please refer to section VS over-voltage (OV) condition.
5	TW	RC	0h	0h = No temperature warning event occurred or the event status got cleared after a READ command was executed on the INT_STAT register. 1h = Temperature warning event occurred or cleared. When the TW bit is flagged to logic 1, it indicates the temperature warning event has occurred. The bit is also flagged to logic 1 when the event clears. For more details about the temperature warning operation, please refer to section Temperature Warning (TW)
4	TSD	RC	0h	0h = No temperature Shutdown event occurred or the event status got cleared after a READ command was executed on the INT_STAT register. 1h = Temperature Shutdown event occurred or cleared. When the TSD bit is flagged to logic 1, it indicates the temperature shutdown event has occurred. The bit is also flagged to logic 1 when the event clears. For more details about the temperature shutdown operation, please refer to section Temperature shutdown (TSD)
3	SSC	RC	0h	0h = No switch state change occurred or the status got cleared after a READ command was executed on the INT_STAT register. 1h = Switch state change occurred. The Switch State Change (SSC) bit indicates whether input threshold crossing has occurred from switch inputs IN0 to IN23. This bit is also flagged to logic 1 after the first polling cycle is completed after device polling is triggered.
2	PRTY_FAIL	RC	0h	0h = No parity error occurred in the last received SI stream or the error status got cleared after a READ command was executed on the INT_STAT register. 1h = Parity error occurred. When the PRTY_FAIL bit is flagged to logic 1, it indicates the last SPI responder in (SI) transaction has a parity error. The device uses odd parity. If the total number of ones in the received data (including the parity bit) is an even number, the received data is discarded. The value of this register bit is mirrored to the PRTY_FLAG SPI status flag.
1	SPI_FAIL	RC	0h	0h = 32 clock pulse during a CS = low sequence was detected or the error status got cleared after a READ command was executed on the INT_STAT register. 1h = SPI error occurred When the SPI_FAIL bit is flagged to logic 1, it indicates the last SPI responder in (SI) transaction is invalid. To program a complete word, 32 bits of information must be entered into the device. The SPI logic counts the number of bits clocked into the IC and enables data latching only if exactly 32 bits have been clocked in. In case the word length exceeds or does not meet the required length, the SPI_FAIL bit is flagged to logic 1, and the data received is considered invalid. The value of this register bit is mirrored to the SPI_FLAG SPI status flag. Note the SPI_FAIL bit is not flagged if SCLK is not present.
0	POR	RC	1h	0h = no Power-On-Reset (POR) event occurred or the status got cleared after a READ command was executed on the INT_STAT register. 1h = Power-On-Reset (POR) event occurred. The Power-On-Reset (POR) interrupt bit indicates whether a reset event has occurred. A reset event sets the registers to their default values and re-initializes the device state machine. This bit is asserted after a successful power-on-reset, hardware reset, or software reset. The value of this register bit is mirrored to the POR SPI status flag.

8.6.3 CRC Register (Offset = 3h) [Reset = FFFFh]

CRC is shown in Figure 8-26 and described in Table 8-14.

Return to Summary Table.

This register returns the CRC-16-CCCIT calculation result. The microcontroller can compare this value with its own calculated value to ensure correct register settings are programmed to the device.

Figure 8-26 CRC Register

23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED								CRC
R-0h								R-FFFFh

LEGEND: R = Read only

Table 8-14 CRC Register Field Descriptions

Bit	Field	Type	Reset	Description
23-16	RESERVED	R	0h	Reserved
15-0	CRC	R	FFFFh	CRC-16-CCITT calculation result: Bit1: LSB of CRC Bit16: MSB or CRC

8.6.4 IN_STAT_MISC Register (Offset = 4h) [Reset = 0h]

IN_STAT_MISC is shown in Figure 8-27 and described in Table 8-15.

Return to Summary Table.

This register indicates current device status unrelated to switch input monitoring.

Figure 8-27 IN_STAT_MISC Register

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED			ADC_D	IN3_D	IN2_D	IN1_D	IN0_D
R-0h			R-0h	R-0h	R-0h	R-0h	R-0h

7	6	5	4	3	2	1	0
VS1_STAT		VS0_STAT		UV_STAT	OV_STAT	TW_STAT	TSD_STAT
R-0h		R-0h		R-0h	R-0h	R-0h	R-0h

Table 8-15 IN_STAT_MISC Register Field Descriptions

Bit	Field	Type	Reset	Description
23-13	RESERVED	R	0h	Reserved
12	ADC_D	R	0h	0h = No error is identified from ADC self-diagnostic. 1h = An error is identified from ADC self-diagnostic.
11	IN3_D	R	0h	0h = Current sink on IN3 is operational. 1h = Current sink on IN3 is abnormal.
10	IN2_D	R	0h	0h = Current sink on IN2 is operational. 1h = Current sink on IN2 is abnormal.
9	IN1_D	R	0h	0h = Current source on IN1 is operational. 1h = Current source on IN1 is abnormal.
8	IN0_D	R	0h	0h = Current source on IN0 is operational. 1h = Current source on IN0 is abnormal.
7-6	VS1_STAT	R	0h	0h = V_S voltage is below threshold VS1_THRES2A. 1h = V_S voltage is below threshold VS1_THRES2B and equal to or above threshold VS1_THRES2A. 2h = V_S voltage is equal to or above threshold VS1_THRES2B. 3h = N/A.
5-4	VS0_STAT	R	0h	0h = V_S voltage is below threshold VS0_THRES2A. 1h = V_S voltage is below threshold VS0_THRES2B and equal to or above threshold VS0_THRES2A. 2h = V_S voltage is equal to or above threshold VS0_THRES2B. 3h = N/A
3	UV_STAT	R	0h	0h = V_S voltage is above the under-voltage condition threshold. 1h = V_S voltage is below the under-voltage condition threshold.
2	OV_STAT	R	0h	0h = V_S voltage is below the over-voltage condition threshold. 1h = V_S voltage is above the over-voltage condition threshold.
1	TW_STAT	R	0h	0h = Device junction temperature is below the temperature warning threshold T_TW. 1h = Device junction temperature is above the temperature warning threshold T_TW.
0	TSD_STAT	R	0h	0h = Device junction temperature is below the temperature shutdown threshold T_TSD. 1h = Device junction temperature is above the temperature shutdown threshold T_TSD.

8.6.5 IN_STAT_COMP Register (Offset = 5h) [Reset = 0h]

IN_STAT_COMP is shown in Figure 8-28 and described in Table 8-16.

Return to Summary Table.

This register indicates whether an input is below or above the comparator threshold when it is configured as comparator input mode.

Figure 8-28 IN_STAT_COMP Register

23	22	21	20	19	18	17	16
INC_23	INC_22	INC_21	INC_20	INC_19	INC_18	INC_17	INC_16
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

15	14	13	12	11	10	9	8
INC_15	INC_14	INC_13	INC_12	INC_11	INC_10	INC_9	INC_8
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

7	6	5	4	3	2	1	0
INC_7	INC_6	INC_5	INC_4	INC_3	INC_2	INC_1	INC_0
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

LEGEND: R = Read only

Table 8-16 IN_STAT_COMP Register Field Descriptions

Bit	Field	Type	Reset	Description
23	INC_23	R	0h	0h = Input IN23 is below the comparator threshold. 1h = Input IN23 is above the comparator threshold.
22	INC_22	R	0h	0h = Input IN22 is below the comparator threshold. 1h = Input IN22 is above the comparator threshold.
21	INC_21	R	0h	0h = Input IN21 is below the comparator threshold. 1h = Input IN21 is above the comparator threshold.
20	INC_20	R	0h	0h = Input IN20 is below the comparator threshold. 1h = Input IN20 is above the comparator threshold.
19	INC_19	R	0h	0h = Input IN19 is below the comparator threshold 1h = Input IN19 is above the comparator threshold
18	INC_18	R	0h	0h = Input IN18 is below the comparator threshold 1h = Input IN18 is above the comparator threshold
17	INC_17	R	0h	0h = Input IN17 is below the comparator threshold 1h = Input IN17 is above the comparator threshold
16	INC_16	R	0h	0h = Input IN16 is below the comparator threshold 1h = Input IN16 is above the comparator threshold
15	INC_15	R	0h	0h = Input IN15 is below the comparator threshold 1h = Input IN15 is above the comparator threshold
14	INC_14	R	0h	0h = Input IN14 is below the comparator threshold 1h = Input IN14 is above the comparator threshold
13	INC_13	R	0h	0h = Input IN13 is below the comparator threshold 1h = Input IN13 is above the comparator threshold
12	INC_12	R	0h	0h = Input IN12 is below the comparator threshold 1h = Input IN12 is above the comparator threshold
11	INC_11	R	0h	0h = Input IN11 is below the comparator threshold 1h = Input IN11 is above the comparator threshold
10	INC_10	R	0h	0h = Input IN10 is below the comparator threshold 1h = Input IN10 is above the comparator threshold
9	INC_9	R	0h	0h = Input IN9 is below the comparator threshold 1h = Input IN9 is above the comparator threshold
8	INC_8	R	0h	0h = Input IN8 is below the comparator threshold 1h = Input IN8 is above the comparator threshold
7	INC_7	R	0h	0h = Input IN7 is below the comparator threshold 1h = Input IN7 is above the comparator threshold
6	INC_6	R	0h	0h = Input IN6 is below the comparator threshold 1h = Input IN6 is above the comparator threshold
5	INC_5	R	0h	0h = Input IN5 is below the comparator threshold 1h = Input IN5 is above the comparator threshold
4	INC_4	R	0h	0h = Input IN4 is below the comparator threshold 1h = Input IN4 is above the comparator threshold
3	INC_3	R	0h	0h = Input IN3 is below the comparator threshold 1h = Input IN3 is above the comparator threshold
2	INC_2	R	0h	0h = Input IN2 is below the comparator threshold 1h = Input IN2 is above the comparator threshold
1	INC_1	R	0h	0h = Input IN1 is below the comparator threshold 1h = Input IN1 is above the comparator threshold
0	INC_0	R	0h	0h = Input IN0 is below the comparator threshold 1h = Input IN0 is above the comparator threshold

8.6.6 IN_STAT_ADC0 Register (Offset = 6h) [Reset = 0h]

IN_STAT_ADC0 is shown in Figure 8-29 and described in Table 8-17.

Return to Summary Table.

This register indicates whether an input is below or above the programmed threshold (for IN0-IN11) when it is configured as ADC input mode. For IN12-IN17, there are 2 thresholds and the register bits indicate whether the input is below, above or in-between the 2 thresholds.

Figure 8-29 IN_STAT_ADC0 Register

23	22	21	20	19	18	17	16
INA_17		INA_16		INA_15		INA_14
R-0h		R-0h		R-0h		R-0h

15	14	13	12	11	10	9	8
INA_13		INA_12		INA_11	INA_10	INA_9	INA_8
R-0h		R-0h		R-0h	R-0h	R-0h	R-0h

7	6	5	4	3	2	1	0
INA_7	INA_6	INA_5	INA_4	INA_3	INA_2	INA_1	INA_0
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

LEGEND: R = Read only

Table 8-17 IN_STAT_ADC0 Register Field Descriptions

Bit	Field	Type	Reset	Description
23-22	INA_17	R	0h	0h = Input IN17 is below threshold 2A 1h = Input IN17 is below threshold 2B and equal to or above threshold 2A 2h = Input IN17 is equal to or above threshold 2B 3h = N/A
21-20	INA_16	R	0h	0h = Input IN16 is below threshold 2A 1h = Input IN16 is below threshold 2B and equal to or above threshold 2A 2h = Input IN16 is equal to or above threshold 2B 3h = N/A
19-18	INA_15	R	0h	0h = Input IN15 is below threshold 2A 1h = Input IN15 is below threshold 2B and equal to or above threshold 2A 2h = Input IN15 is equal to or above threshold 2B 3h = N/A
17-16	INA_14	R	0h	0h = Input IN14 is below threshold 2A 1h = Input IN14 is below threshold 2B and equal to or above threshold 2A 2h = Input IN14 is equal to or above threshold 2B 3h = N/A
15-14	INA_13	R	0h	0h = Input IN13 is below threshold 2A 1h = Input IN13 is below threshold 2B and equal to or above threshold 2A 2h = Input IN13 is equal to or above threshold 2B 3h = N/A
13-12	INA_12	R	0h	0h = Input IN12 is below threshold 2A 1h = Input IN12 is below threshold 2B and equal to or above threshold 2A 2h = Input IN12 is equal to or above threshold 2B 3h = N/A
11	INA_11	R	0h	0h = Input IN11 is below configured threshold 1h = Input IN11 is above configured threshold
10	INA_10	R	0h	0h = Input IN10 is below configured threshold 1h = Input IN10 is above configured threshold
9	INA_9	R	0h	0h = Input IN9 is below configured threshold 1h = Input IN9 is above configured threshold
8	INA_8	R	0h	0h = Input IN8 is below configured threshold 1h = Input IN8 is above configured threshold
7	INA_7	R	0h	0h = Input IN7 is below configured threshold 1h = Input IN7 is above configured threshold
6	INA_6	R	0h	0h = Input IN6 is below configured threshold 1h = Input IN6 is above configured threshold
5	INA_5	R	0h	0h = Input IN5 is below configured threshold 1h = Input IN5 is above configured threshold
4	INA_4	R	0h	0h = Input IN4 is below configured threshold 1h = Input IN4 is above configured threshold
3	INA_3	R	0h	0h = Input IN3 is below configured threshold 1h = Input IN3 is above configured threshold
2	INA_2	R	0h	0h = Input IN2 is below configured threshold 1h = Input IN2 is above configured threshold
1	INA_1	R	0h	0h = Input IN1 is below configured threshold 1h = Input IN1 is above configured threshold
0	INA_0	R	0h	0h = Input IN0 is below configured threshold 1h = Input IN0 is above configured threshold

8.6.7 IN_STAT_ADC1 Register (Offset = 7h) [Reset = 0h]

IN_STAT_ADC1 is shown in Figure 8-30 and described in Table 8-18.

Return to Summary Table.

This register indicates whether an input is above or below the programmed thresholds 3A, 3B, and 3C when it is configured as ADC input mode. For IN23, there are 5 thresholds that can be programmed.

Figure 8-30 IN_STAT_ADC1 Register

23	22	21	20	19	18	17	16	15	14	13	12
RESERVED											INA_23
R-0h											R-0h

11	10	9	8	7	6	5	4	3	2	1	0
INA_23		INA_22		INA_21		INA_20		INA_19		INA_18
R-0h		R-0h		R-0h		R-0h		R-0h		R-0h

LEGEND: R = Read only

Table 8-18 IN_STAT_ADC1 Register Field Descriptions

Bit	Field	Type	Reset	Description
23-13	RESERVED	R	0h	Reserved
12-10	INA_23	R	0h	0h = Input IN23 is below threshold 3A 1h = Input IN23 is below threshold 3B and equal to or above threshold 3A 2h = Input IN23 is below threshold 3C and equal to or above threshold 3B 3h = Input IN23 is below threshold THRES8 and equal to or above threshold 3C 4h = Input IN23 is below threshold THRES9 and equal to or above threshold THRES8 5h = Input IN23 is equal to or above threshold THRES9
9-8	INA_22	R	0h	0h = Input IN22 is below threshold 3A 1h = Input IN22 is below threshold 3B and equal to or above threshold 3A 2h = Input IN22 is below threshold 3C and equal to or above threshold 3B 3h = Input IN22 is equal to or above threshold 3C
7-6	INA_21	R	0h	0h = Input IN21 is below threshold 3A 1h = Input IN21 is below threshold 3B and equal to or above threshold 3A 2h = Input IN21 is below threshold 3C and equal to or above threshold 3B 3h = Input IN21 is equal to or above threshold 3C
5-4	INA_20	R	0h	0h = Input IN20 is below threshold 3A 1h = Input IN20 is below threshold 3B and equal to or above threshold 3A 2h = Input IN20 is below threshold 3C and equal to or above threshold 3B 3h = Input IN20 is equal to or above threshold 3C
3-2	INA_19	R	0h	0h = Input IN19 is below threshold 3A 1h = Input IN19 is below threshold 3B and equal to or above threshold 3A 2h = Input IN19 is below threshold 3C and equal to or above threshold 3B 3h = Input IN19 is equal to or above threshold 3C
1-0	INA_18	R	0h	0h = Input is IN18 is below threshold 3A 1h = Input is IN18 is below threshold 3B and equal to or above threshold 3A 2h = Input is IN18 is below threshold 3C and equal to or above threshold 3B 3h = Input is IN18 is equal to or above threshold 3C

8.6.8 IN_STAT_MATRIX0 Register (Offset = 8h) [Reset = 0h]

IN_STAT_MATRIX0 is shown in Figure 8-31 and described in Table 8-19.

Return to Summary Table.

This register indicates whether an input is below or above the programmed threshold in the matrix polling mode for switches connected to IN10-IN13.

Figure 8-31 IN_STAT_MATRIX0 Register

23	22	21	20	19	18	17	16
INMAT_13_IN9	INMAT_13_IN8	INMAT_13_IN7	INMAT_13_IN6	INMAT_13_IN5	INMAT_13_IN4	INMAT_12_IN9	INMAT_12_IN8
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

15	14	13	12	11	10	9	8
INMAT_12_IN7	INMAT_12_IN6	INMAT_12_IN5	INMAT_12_IN4	INMAT_11_IN9	INMAT_11_IN8	INMAT_11_IN7	INMAT_11_IN6
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

7	6	5	4	3	2	1	0
INMAT_11_IN5	INMAT_11_IN4	INMAT_10_IN9	INMAT_10_IN8	INMAT_10_IN7	INMAT_10_IN6	INMAT_10_IN5	INMAT_10_IN4
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

LEGEND: R = Read only

Table 8-19 IN_STAT_MATRIX0 Register Field Descriptions

Bit	Field	Type	Reset	Description
23	INMAT_13_IN9	R	0h	0h = Input IN13 is below threshold while IN9 pulled to GND 1h = Input IN13 is above threshold while IN9 pulled to GND
22	INMAT_13_IN8	R	0h	0h = Input IN13 is below threshold while IN8 pulled to GND 1h = Input IN13 is above threshold while IN8 pulled to GND
21	INMAT_13_IN7	R	0h	0h = Input IN13 is below threshold while IN7 pulled to GND 1h = Input IN13 is above threshold while IN7 pulled to GND
20	INMAT_13_IN6	R	0h	0h = Input IN13 is below threshold while IN6 pulled to GND 1h = Input IN13 is above threshold while IN6 pulled to GND
19	INMAT_13_IN5	R	0h	0h = Input IN13 is below threshold while IN5 pulled to GND 1h = Input IN13 is above threshold while IN5 pulled to GND
18	INMAT_13_IN4	R	0h	0h = Input IN13 is below threshold while IN4 pulled to GND 1h = Input IN13 is above threshold while IN4 pulled to GND
17	INMAT_12_IN9	R	0h	0h = Input IN12 is below threshold while IN9 pulled to GND 1h = Input IN12 is above threshold while IN9 pulled to GND
16	INMAT_12_IN8	R	0h	0h = Input IN12 is below threshold while IN8 pulled to GND. 1h = Input IN12 is above threshold while IN8 pulled to GND.
15	INMAT_12_IN7	R	0h	0h = Input IN12 is below threshold while IN7 pulled to GND. 1h = Input IN12 is above threshold while IN7 pulled to GND.
14	INMAT_12_IN6	R	0h	0h = Input IN12 is below threshold while IN6 pulled to GND. 1h = Input IN12 is above threshold while IN6 pulled to GND.
13	INMAT_12_IN5	R	0h	0h = Input IN12 is below threshold while IN5 pulled to GND. 1h = Input IN12 is above threshold while IN5 pulled to GND.
12	INMAT_12_IN4	R	0h	0h = Input IN12 is below threshold while IN4 pulled to GND. 1h = Input IN12 is above threshold while IN4 pulled to GND.
11	INMAT_11_IN9	R	0h	0h = Input IN11 is below threshold while IN9 pulled to GND. 1h = Input IN11 is above threshold while IN9 pulled to GND.
10	INMAT_11_IN8	R	0h	0h = Input IN11 is below threshold while IN8 pulled to GND. 1h = Input IN11 is above threshold while IN8 pulled to GND.
9	INMAT_11_IN7	R	0h	0h = Input IN11 is below threshold while IN7 pulled to GND. 1h = Input IN11 is above threshold while IN7 pulled to GND.
8	INMAT_11_IN6	R	0h	0h = Input IN11 is below threshold while IN6 pulled to GND. 1h = Input IN11 is above threshold while IN6 pulled to GND.
7	INMAT_11_IN5	R	0h	0h = Input IN11 is below threshold while IN5 pulled to GND. 1h = Input IN11 is above threshold while IN5 pulled to GND.
6	INMAT_11_IN4	R	0h	0h = Input IN11 is below threshold while IN4 pulled to GND. 1h = Input IN11 is above threshold while IN4 pulled to GND.
5	INMAT_10_IN9	R	0h	0h = Input IN10 is below threshold while IN9 pulled to GND. 1h = Input IN10 is above threshold while IN9 pulled to GND.
4	INMAT_10_IN8	R	0h	0h = Input IN10 is below threshold while IN8 pulled to GND. 1h = Input IN10 is above threshold while IN8 pulled to GND.
3	INMAT_10_IN7	R	0h	0h = Input IN10 is below threshold while IN7 pulled to GND. 1h = Input IN10 is above threshold while IN7 pulled to GND.
2	INMAT_10_IN6	R	0h	0h = Input IN10 is below threshold while IN6 pulled to GND. 1h = Input IN10 is above threshold while IN6 pulled to GND.
1	INMAT_10_IN5	R	0h	0h = Input IN10 is below threshold while IN5 pulled to GND. 1h = Input IN10 is above threshold while IN5 pulled to GND.
0	INMAT_10_IN4	R	0h	0h = Input IN10 is below threshold while IN4 pulled to GND. 1h = Input IN10 is above threshold while IN4 pulled to GND.

8.6.9 IN_STAT_MATRIX1 Register (Offset = 9h) [Reset = 0h]

IN_STAT_MATRIX1 is shown in Figure 8-32 and described in Table 8-20.

Return to Summary Table.

This register indicates whether an input is below or above the programmed threshold in the matrix polling mode for switches connected to IN14-IN15. This register also indicates the status of IN0-IN11 with respect to the common threshold THRES_COM.

Figure 8-32 IN_STAT_MATRIX1 Register

23	22	21	20	19	18	17	16
IN11_COM	IN10_COM	IN9_COM	IN8_COM	IN7_COM	IN6_COM	IN5_COM	IN4_COM
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

15	14	13	12	11	10	9	8
IN3_COM	IN2_COM	IN1_COM	IN0_COM	INMAT_15_IN9	INMAT_15_IN8	INMAT_15_IN7	INMAT_15_IN6
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

7	6	5	4	3	2	1	0
INMAT_15_IN5	INMAT_15_IN4	INMAT_14_IN9	INMAT_14_IN8	INMAT_14_IN7	INMAT_14_IN6	INMAT_14_IN5	INMAT_14_IN4
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

LEGEND: R = Read only

Table 8-20 IN_STAT_MATRIX1 Register Field Descriptions

Bit	Field	Type	Reset	Description
23	IN11_COM	R	0h	0h = Input IN11 below threshold THRES_COM 1h = Input IN11 equal to or above threshold THRES_COM
22	IN10_COM	R	0h	0h = Input IN10 below threshold THRES_COM 1h = Input IN10 equal to or above threshold THRES_COM
21	IN9_COM	R	0h	0h = Input IN9 below threshold THRES_COM 1h = Input IN9 equal to or above threshold THRES_COM
20	IN8_COM	R	0h	0h = Input IN8 below threshold THRES_COM 1h = Input IN8 equal to or above threshold THRES_COM
19	IN7_COM	R	0h	0h = Input IN7 below threshold THRES_COM 1h = Input IN7 equal to or above threshold THRES_COM
18	IN6_COM	R	0h	0h = Input IN6 below threshold THRES_COM 1h = Input IN6 equal to or above threshold THRES_COM
17	IN5_COM	R	0h	0h = Input IN5 below threshold THRES_COM 1h = Input IN5 equal to or above threshold THRES_COM
16	IN4_COM	R	0h	0h = Input IN4 below threshold THRES_COM 1h = Input IN4 equal to or above threshold THRES_COM
15	IN3_COM	R	0h	0h = Input IN3 below threshold THRES_COM 1h = Input IN3 equal to or above threshold THRES_COM
14	IN2_COM	R	0h	0h = Input IN2 below threshold THRES_COM 1h = Input IN2 equal to or above threshold THRES_COM
13	IN1_COM	R	0h	0h = Input IN1 below threshold THRES_COM 1h = Input IN1 equal to or above threshold THRES_COM
12	IN0_COM	R	0h	0h = Input IN0 below threshold THRES_COM 1h = Input IN0 equal to or above threshold THRES_COM
11	INMAT_15_IN9	R	0h	0h = Input IN15 below threshold while IN9 pulled to GND 1h = Input IN15 above threshold while IN9 pulled to GND
10	INMAT_15_IN8	R	0h	0h = Input IN15 below threshold while IN8 pulled to GND 1h = Input IN15 above threshold while IN8 pulled to GND
9	INMAT_15_IN7	R	0h	0h = Input IN15 below threshold while IN7 pulled to GND 1h = Input IN15 above threshold while IN7 pulled to GND
8	INMAT_15_IN6	R	0h	0h = Input IN15 below threshold while IN6 pulled to GND 1h = Input IN15 above threshold while IN6 pulled to GND
7	INMAT_15_IN5	R	0h	0h = Input IN15 below threshold while IN5 pulled to GND 1h = Input IN15 above threshold while IN5 pulled to GND
6	INMAT_15_IN4	R	0h	0h = Input IN15 below threshold while IN4 pulled to GND 1h = Input IN15 above threshold while IN4 pulled to GND
5	INMAT_14_IN9	R	0h	0h = Input IN14 below threshold while IN9 pulled to GND 1h = Input IN14 above threshold while IN9 pulled to GND
4	INMAT_14_IN8	R	0h	0h = Input IN14 below threshold while IN8 pulled to GND 1h = Input IN14 above threshold while IN8 pulled to GND
3	INMAT_14_IN7	R	0h	0h = Input IN14 below threshold while IN7 pulled to GND 1h = Input IN14 above threshold while IN7 pulled to GND
2	INMAT_14_IN6	R	0h	0h = Input IN14 below threshold while IN6 pulled to GND 1h = Input IN14 above threshold while IN6 pulled to GND
1	INMAT_14_IN5	R	0h	0h = Input IN14 below threshold while IN5 pulled to GND 1h = Input IN14 above threshold while IN5 pulled to GND
0	INMAT_14_IN4	R	0h	0h = Input IN14 below threshold while IN4 pulled to GND 1h = Input IN14 above threshold while IN4 pulled to GND

8.6.10 ANA_STAT0 Register (Offset = Ah) [Reset = 0h]

ANA_STAT0 is shown in Figure 8-33 and described in Table 8-21.

Return to Summary Table.

Figure 8-33 ANA_STAT0 Register

23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED				IN1_ANA										IN0_ANA
R-0h				R-0h										R-0h

LEGEND: R = Read only

Table 8-21 ANA_STAT0 Register Field Descriptions

Bit	Field	Type	Reset	Description
23-20	RESERVED	R	0h	Reserved
19-10	IN1_ANA	R	0h	10-bits value of IN1 Bit 10: LSB Bit 19: MSB
9-0	IN0_ANA	R	0h	10-bits value of IN0 Bit 0: LSB Bit 9: MSB

Bit

Field

Type

Reset

Description

23-20

RESERVED

Reserved

19-10

IN1_ANA

10-bits value of IN1

Bit 10: LSB

Bit 19: MSB

9-0

IN0_ANA

10-bits value of IN0

Bit 0: LSB

Bit 9: MSB

8.6.11 ANA_STAT1 Register (Offset = Bh) [Reset = 0h]

ANA_STAT1 is shown in Figure 8-34 and described in Table 8-22.

Return to Summary Table.

Figure 8-34 ANA_STAT1 Register

23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED				IN5_ANA										IN4_ANA
R-0h				R-0h										R-0h

LEGEND: R = Read only

Table 8-22 ANA_STAT1 Register Field Descriptions

Bit	Field	Type	Reset	Description
23-20	RESERVED	R	0h	Reserved
19-10	IN3_ANA	R	0h	10-bits value of IN3 Bit 10: LSB Bit 19: MSB
9-0	IN2_ANA	R	0h	10-bits value of IN2 Bit 0: LSB Bit 9: MSB

Bit

Field

Type

Reset

Description

23-20

RESERVED

Reserved

19-10

IN3_ANA

10-bits value of IN3

Bit 10: LSB

Bit 19: MSB

9-0

IN2_ANA

10-bits value of IN2

Bit 0: LSB

Bit 9: MSB

8.6.12 ANA_STAT2 Register (Offset = Ch) [Reset = 0h]

ANA_STAT2 is shown in Figure 8-35 and described in Table 8-23.

Return to Summary Table.

Figure 8-35 ANA_STAT2 Register

23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED				IN5_ANA										IN4_ANA
R-0h				R-0h										R-0h

LEGEND: R = Read only

Table 8-23 ANA_STAT2 Register Field Descriptions

Bit	Field	Type	Reset	Description
23-20	RESERVED	R	0h	Reserved
19-10	IN5_ANA	R	0h	10-bits value of IN5 Bit 10: LSB Bit 19: MSB
9-0	IN4_ANA	R	0h	10-bits value of IN4 Bit 0: LSB Bit 9: MSB

Bit

Field

Type

Reset

Description

23-20

RESERVED

Reserved

19-10

IN5_ANA

10-bits value of IN5

Bit 10: LSB

Bit 19: MSB

9-0

IN4_ANA

10-bits value of IN4

Bit 0: LSB

Bit 9: MSB

8.6.13 ANA_STAT3 Register (Offset = Dh) [Reset = 0h]

ANA_STAT3 is shown in Figure 8-36 and described in Table 8-24.

Return to Summary Table.

Figure 8-36 ANA_STAT3 Register

23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED				IN7_ANA										IN6_ANA
R-0h				R-0h										R-0h

LEGEND: R = Read only

Table 8-24 ANA_STAT3 Register Field Descriptions

Bit	Field	Type	Reset	Description
23-20	RESERVED	R	0h	Reserved
19-10	IN7_ANA	R	0h	10-bits value of IN7 Bit 10: LSB Bit 19: MSB
9-0	IN6_ANA	R	0h	10-bits value of IN6 Bit 0: LSB Bit 9: MSB

Bit

Field

Type

Reset

Description

23-20

RESERVED

Reserved

19-10

IN7_ANA

10-bits value of IN7

Bit 10: LSB

Bit 19: MSB

9-0

IN6_ANA

10-bits value of IN6

Bit 0: LSB

Bit 9: MSB

8.6.14 ANA_STAT4 Register (Offset = Eh) [Reset = 0h]

ANA_STAT4 is shown in Figure 8-37 and described in Table 8-25.

Return to Summary Table.

Figure 8-37 ANA_STAT4 Register

23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED				IN9_ANA										IN8_ANA
R-0h				R-0h										R-0h

LEGEND: R = Read only

Table 8-25 ANA_STAT4 Register Field Descriptions

Bit	Field	Type	Reset	Description
23-20	RESERVED	R	0h	Reserved
19-10	IN9_ANA	R	0h	10-bits value of IN9 Bit 10: LSB Bit 19: MSB
9-0	IN8_ANA	R	0h	10-bits value of IN8 Bit 0: LSB Bit 9: MSB

Bit

Field

Type

Reset

Description

23-20

RESERVED

Reserved

19-10

IN9_ANA

10-bits value of IN9

Bit 10: LSB

Bit 19: MSB

9-0

IN8_ANA

10-bits value of IN8

Bit 0: LSB

Bit 9: MSB

8.6.15 ANA_STAT5 Register (Offset = Fh) [Reset = 0h]

ANA_STAT5 is shown in Figure 8-38 and described in Table 8-26.

Return to Summary Table.

Figure 8-38 ANA_STAT5 Register

23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED				IN11_ANA										IN10_ANA
R-0h				R-0h										R-0h

LEGEND: R = Read only

Table 8-26 ANA_STAT5 Register Field Descriptions

Bit	Field	Type	Reset	Description
23-20	RESERVED	R	0h	Reserved
19-10	IN11_ANA	R	0h	10-bits value of IN11 Bit 10: LSB Bit 19: MSB
9-0	IN10_ANA	R	0h	10-bits value of IN10 Bit 0: LSB Bit 9: MSB

Bit

Field

Type

Reset

Description

23-20

RESERVED

Reserved

19-10

IN11_ANA

10-bits value of IN11

Bit 10: LSB

Bit 19: MSB

9-0

IN10_ANA

10-bits value of IN10

Bit 0: LSB

Bit 9: MSB

8.6.16 ANA_STAT6 Register (Offset = 10h) [reset = 0h]

ANA_STAT6 is shown in Figure 8-39 and described in Table 8-27.

Return to Summary Table.

Figure 8-39 ANA_STAT6 Register

23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED				IN13_ANA										IN12_ANA
R-0h				R-0h										R-0h

LEGEND: R = Read only

Table 8-27 ANA_STAT6 Register Field Descriptions

Bit	Field	Type	Reset	Description
23-20	RESERVED	R	0h	Reserved
19-10	IN13_ANA	R	0h	10-bits value of IN13 Bit 10: LSB Bit 19: MSB
9-0	IN12_ANA	R	0h	10-bits value of IN12 Bit 0: LSB Bit 9: MSB

Bit

Field

Type

Reset

Description

23-20

RESERVED

Reserved

19-10

IN13_ANA

10-bits value of IN13

Bit 10: LSB

Bit 19: MSB

9-0

IN12_ANA

10-bits value of IN12

Bit 0: LSB

Bit 9: MSB

8.6.17 ANA_STAT7 Register (Offset = 11h) [Reset = 0h]

ANA_STAT7 is shown in Figure 8-40 and described in Table 8-28.

Return to Summary Table.

Figure 8-40 ANA_STAT7 Register

23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED				IN15_ANA										IN14_ANA
R-0h				R-0h										R-0h

LEGEND: R = Read only

Table 8-28 ANA_STAT7 Register Field Descriptions

Bit

Field

Type

Reset

Description

23-20

RESERVED

Reserved

19-10

IN15_ANA

10-bits value of IN15

Bit 10: LSB

Bit 19: MSB

9-0

IN14_ANA

10-bits value of IN14

Bit 0: LSB

Bit 9: MSB

8.6.18 ANA_STAT8 Register (Offset = 12h) [Reset = 0h]

ANA_STAT8 is shown in Figure 8-41 and described in Table 8-29.

Return to Summary Table.

Figure 8-41 ANA_STAT8 Register

23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED				IN17_ANA										IN16_ANA
R-0h				R-0h										R-0h

LEGEND: R = Read only

Table 8-29 ANA_STAT8 Register Field Descriptions

Bit

Field

Type

Reset

Description

23-20

RESERVED

Reserved

19-10

IN17_ANA

10-bits value of IN17

Bit 10: LSB

Bit 19: MSB

9-0

IN16_ANA

10-bits value of IN16

Bit 0: LSB

Bit 9: MSB

8.6.19 ANA_STAT9 Register (Offset = 13h) [Reset = 0h]

ANA_STAT9 is shown in Figure 8-42 and described in Table 8-30.

Return to Summary Table.

Figure 8-42 ANA_STAT9 Register

23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED				IN19_ANA										IN18_ANA
R-0h				R-0h										R-0h

LEGEND: R = Read only

Table 8-30 ANA_STAT9 Register Field Descriptions

Bit

Field

Type

Reset

Description

23-20

RESERVED

Reserved

19-10

IN19_ANA

10-bits value of IN19

Bit 10: LSB

Bit 19: MSB

9-0

IN18_ANA

10-bits value of IN18

Bit 0: LSB

Bit 9: MSB

8.6.20 ANA_STAT10 Register (Offset = 14h) [Reset = 0h]

ANA_STAT10 is shown in Figure 8-43 and described in Table 8-31.

Return to Summary Table.

Figure 8-43 ANA_STAT10 Register

23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED				IN21_ANA										IN20_ANA
R-0h				R-0h										R-0h

LEGEND: R = Read only

Table 8-31 ANA_STAT10 Register Field Descriptions

Bit

Field

Type

Reset

Description

23-20

RESERVED

Reserved

19-10

IN21_ANA

10-bits value of IN21

Bit 10: LSB

Bit 19: MSB

9-0

IN20_ANA

10-bits value of IN20

Bit 0: LSB

Bit 9: MSB

8.6.21 ANA_STAT11 Register (Offset = 15h) [Reset = 0h]

ANA_STAT11 is shown in Figure 8-44 and described in Table 8-32.

Return to Summary Table.

Figure 8-44 ANA_STAT11 Register

23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED				IN23_ANA										IN22_ANA
R-0h				R-0h										R-0h

LEGEND: R = Read only

Table 8-32 ANA_STAT11 Register Field Descriptions

Bit

Field

Type

Reset

Description

23-20

RESERVED

Reserved

19-10

IN23_ANA

10-bits value of IN23

Bit 10: LSB

Bit 19: MSB

9-0

IN22_ANA

10-bits value of IN22

Bit 0: LSB

Bit 9: MSB

8.6.22 ANA_STAT12 Register (Offset = 16h) [Reset = 0h]

ANA_STAT12 is shown in Figure 8-45 and described in Table 8-33.

Return to Summary Table.

Figure 8-45 ANA_STAT12 Register

23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED				ADC_SELF_ANA										V_S_ANA
R-0h				R-0h										R-0h

LEGEND: R = Read only

Table 8-33 ANA_STAT12 Register Field Descriptions

Bit

Field

Type

Reset

Description

23-20

RESERVED

Reserved

19-10

ADC_SELF_ANA

10-bits value of the ADC self-diagnosis

Bit 10: LSB

Bit 19: MSB

9-0

V_S_ANA

10-bits value of V_S measurement

Bit 0: LSB

Bit 9: MSB

8.6.23 CONFIG Register (Offset = 1Ah) [Reset = 0h]

CONFIG is shown in Figure 8-46 and described in Table 8-34.

Return to Summary Table.

Figure 8-46 CONFIG Register

23	22	21	20	19	18	17	16
VS_RATIO	ADC_DIAG_T	WET_D_IN3_EN	WET_D_IN2_EN	WET_D_IN1_EN	WET_D_IN0_EN	VS_MEAS_EN	TW_CUR_DIS_CSI
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

15	14	13	12	11	10	9	8
DET_FILTER		TW_CUR_DIS_CSO	INT_CONFIG	TRIGGER	POLL_EN	CRC_T	POLL_ACT_TIME
R/W-0h		R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

7	6	5	4	3	2	1	0
POLL_ACT_TIME			POLL_TIME				RESET
R/W-0h			R/W-0h				R/W-0h

LEGEND: R/W = Read/Write

Table 8-34 CONFIG Register Field Descriptions

Bit	Field	Type	Reset	Description
23	VS_RATIO	R/W	0h	0h = Use voltage divider factor of 3 for the V_S measurement 1h = Use voltage divider factor of 10 for the V_S measurement
22	ADC_DIAG_T	R/W	0h	For detailed descriptions for the ADC self-diagnostic feature, refer to section ADC Self-Diagnostic 0h = Disable ADC self-diagnostic feature 1h = Enable ADC self-diagnostic feature
21	WET_D_IN3_EN	R/W	0h	0h = Disable wetting current diagnostic for input IN3 1h = Enable wetting current diagnostic for input IN3
20	WET_D_IN2_EN	R/W	0h	0h = Disable wetting current diagnostic for input IN2 1h = Enable wetting current diagnostic for input IN2
19	WET_D_IN1_EN	R/W	0h	0h = Disable wetting current diagnostic for input IN1 1h = Enable wetting current diagnostic for input IN1
18	WET_D_IN0_EN	R/W	0h	0h = Disable wetting current diagnostic for input IN0 1h = Enable wetting current diagnostic for input IN0
17	VS_MEAS_EN	R/W	0h	For detailed descriptions for the V_S measurement, refer to section VS Measurement. 0h = Disable V_S measurement at the end of every polling cycle 1h = Enable V_S measurement at the end of every polling cycle
16	TW_CUR_DIS_CSI	R/W	0h	0h = Enable wetting current reduction (to 2 mA) for 10 mA and 15 mA settings upon TW event for all inputs enabled with CSI. 1h = Disable wetting current reduction (to 2 mA) for 10 mA and 15 mA settings upon TW event for all inputs enabled with CSI.
15-14	DET_FILTER	R/W	0h	For detailed descriptions for the detection filter, refer to section Detection Filter. 0h = every sample is valid and taken for threshold evaluation 1h = 2 consecutive and equal samples required to be valid data 2h = 3 consecutive and equal samples required to be valid data 3h = 4 consecutive and equal samples required to be valid data
13	TW_CUR_DIS_CSO	R/W	0h	0h = Enable wetting current reduction (to 2 mA) for 10 mA and 15 mA settings upon TW event for all inputs enabled with CSO. 1h = Disable wetting current reduction (to 2 mA) for 10 mA and 15 mA settings upon TW event for all inputs enabled with CSO.
12	INT_CONFIG	R/W	0h	For detailed descriptions for the INT pin assertion scheme, refer to section Interrupt Generation and /INT Assertion. 0h = INT pin assertion scheme set to static 1h = INT pin assertion scheme set to dynamic
11	TRIGGER	R/W	0h	When the TRIGGER bit is set to logic 1, normal device operation (wetting current activation and polling) starts. To stop device operation and keep the device in an idle state, de-assert this bit to 0. After device normal operation is triggered, if at any time the device setting needs to be re-configured, the microcontroller is required to first set the bit TRIGGER to logic 0 to stop device operation. Once the re-configuration is completed, the microcontroller can set the TRIGGER bit back to logic 1 to re-start device operation. If re-configuration is done on the fly without first stopping the device operation, false switch status could be reported and accidental interrupt might be issued. The following register bits are the exception and can be configured when TRIGGER bit is set to logic 1: TRIGGER (bit 11 of the CONFIG register) CRC_T (bit 9 of the CONFIG register) RESET (bit 0 of the CONFIG register) The CCP_CFG1 register 0h = Stop TIC12400-Q1 from normal operation. 1h = Trigger TIC12400-Q1 from normal operation.
10	POLL_EN	R/W	0h	0h = Polling disabled. Device operates in continuous mode. 1h = Polling enabled and the device operates in one of the polling modes.
9	CRC_T	R/W	0h	Set this bit to 1 to trigger a CRC calculation on all the configuration register bits. Once triggered, it is strongly recommended the SPI controller does not change the content of the configuration registers until the CRC calculation is completed to avoid erroneous CRC calculation result. The TIC12400-Q1 sets the CRC_CALC interrupt bit and asserts the INT pin low when the CRC calculation is completed. The calculated result will be available in the CRC register. This bit self-clears back to 0 after CRC calculation is executed. 0h = no CRC calculation triggered. 1h = trigger CRC calculation.
8-5	POLL_ACT_TIME	R/W	0h	0h = 64 μs 1h = 128 μs 2h = 192 μs 3h = 256 μs 4h = 320 μs 5h = 384 μs 6h = 448 μs 7h = 512 μs 8h = 640 μs 9h = 768 μs Ah = 896 μs Bh = 1024 μs Ch = 2048 μs Dh-15h = 512 μs (most frequently-used setting)
4-1	POLL_TIME	R/W	0h	0h = 2 ms 1h = 4 ms 2h = 8 ms 3h = 16 ms 4h = 32 ms 5h = 48 ms 6h = 64 ms 7h = 128 ms 8h = 256 ms 9h = 512 ms Ah = 1024 ms Bh = 2048 ms Ch = 4096 ms Dh-15h = 8 ms (most frequently-used setting)
0	RESET	R/W	0h	0h = No reset. 1h = Trigger software reset of the device.

8.6.24 IN_EN Register (Offset = 1Bh) [Reset = 0h]

IN_EN is shown in Figure 8-47 and described in Table 8-35.

Return to Summary Table.

Figure 8-47 IN_EN Register

23	22	21	20	19	18	17	16
IN_EN_23	IN_EN_22	IN_EN_21	IN_EN_20	IN_EN_19	IN_EN_18	IN_EN_17	IN_EN_16
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

15	14	13	12	11	10	9	8
IN_EN_15	IN_EN_14	IN_EN_13	IN_EN_12	IN_EN_11	IN_EN_10	IN_EN_9	IN_EN_8
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

7	6	5	4	3	2	1	0
IN_EN_7	IN_EN_6	IN_EN_5	IN_EN_4	IN_EN_3	IN_EN_2	IN_EN_1	IN_EN_0
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

LEGEND: R/W = Read/Write

Table 8-35 IN_EN Register Field Descriptions

Bit	Field	Type	Reset	Description
23	IN_EN_23	R/W	0h	0h = Input channel IN23 disabled. Polling sequence skips this channel 1h = Input channel IN23 enabled.
22	IN_EN_22	R/W	0h	0h = Input channel IN22 disabled. Polling sequence skips this channel 1h = Input channel IN22 enabled.
21	IN_EN_21	R/W	0h	0h = Input channel IN21 disabled. Polling sequence skips this channel 1h = Input channel IN21 enabled.
20	IN_EN_20	R/W	0h	0h = Input channel IN20 disabled. Polling sequence skips this channel 1h = Input channel IN20 enabled.
19	IN_EN_19	R/W	0h	0h = Input channel IN19 disabled. Polling sequence skips this channel 1h = Input channel IN19 enabled.
18	IN_EN_18	R/W	0h	0h = Input channel IN18 disabled. Polling sequence skips this channel 1h = Input channel IN18 enabled.
17	IN_EN_17	R/W	0h	0h = Input channel IN17 disabled. Polling sequence skips this channel 1h = Input channel IN17 enabled.
16	IN_EN_16	R/W	0h	0h = Input channel IN16 disabled. Polling sequence skips this channel 1h = Input channel IN16 enabled.
15	IN_EN_15	R/W	0h	0h = Input channel IN15 disabled. Polling sequence skips this channel 1h = Input channel IN15 enabled.
14	IN_EN_14	R/W	0h	0h = Input channel IN14 disabled. Polling sequence skips this channel 1h = Input channel IN14 enabled.
13	IN_EN_13	R/W	0h	0h = Input channel IN13 disabled. Polling sequence skips this channel 1h = Input channel IN13 enabled.
12	IN_EN_12	R/W	0h	0h = Input channel IN12 disabled. Polling sequence skips this channel 1h = Input channel IN12 enabled.
11	IN_EN_11	R/W	0h	0h = Input channel IN11 disabled. Polling sequence skips this channel 1h = Input channel IN11 enabled.
10	IN_EN_10	R/W	0h	0h = Input channel IN10 disabled. Polling sequence skips this channel 1h = Input channel IN10 enabled.
9	IN_EN_9	R/W	0h	0h = Input channel IN9 disabled. Polling sequence skips this channel 1h = Input channel IN9 enabled.
8	IN_EN_8	R/W	0h	0h = Input channel IN8 disabled. Polling sequence skips this channel 1h = Input channel IN8 enabled.
7	IN_EN_7	R/W	0h	0h = Input channel IN7 disabled. Polling sequence skips this channel 1h = Input channel IN7 enabled.
6	IN_EN_6	R/W	0h	0h = Input channel IN6 disabled. Polling sequence skips this channel 1h = Input channel IN6 enabled.
5	IN_EN_5	R/W	0h	0h = Input channel IN5 disabled. Polling sequence skips this channel 1h = Input channel IN5 enabled.
4	IN_EN_4	R/W	0h	0h = Input channel IN4 disabled. Polling sequence skips this channel 1h = Input channel IN4 enabled.
3	IN_EN_3	R/W	0h	0h = Input channel IN3 disabled. Polling sequence skips this channel 1h = Input channel IN3 enabled.
2	IN_EN_2	R/W	0h	0h = Input channel IN2 disabled. Polling sequence skips this channel 1h = Input channel IN2 enabled.
1	IN_EN_1	R/W	0h	0h = Input channel IN1 disabled. Polling sequence skips this channel 1h = Input channel IN1 enabled.
0	IN_EN_0	R/W	0h	0h = Input channel IN0 disabled. Polling sequence skips this channel 1h = Input channel IN0 enabled.

8.6.25 CS_SELECT Register (Offset = 1Ch) [Reset = 0h]

CS_SELECT is shown in Figure 8-48 and described in Table 8-36.

Return to Summary Table.

Figure 8-48 CS_SELECT Register

23	22	21	20	19	18	17	16	15	14	13	12
RESERVED
R-0h
11	10	9	8	7	6	5	4	3	2	1	0
RESERVED		CS_IN9	CS_IN8	CS_IN7	CS_IN6	CS_IN5	CS_IN4	CS_IN3	CS_IN2	CS_IN1	CS_IN0
R-0h		R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

LEGEND: R/W = Read/Write; R = Read only

Table 8-36 CS_SELECT Register Field Descriptions

Bit	Field	Type	Reset	Description
23-10	RESERVED	R	0h	Reserved
9	CS_IN9	R/W	0h	0h = Current Source (CSO) selected 1h = Current Sink (CSI) selected
8	CS_IN8	R/W	0h	0h = Current Source (CSO) selected 1h = Current Sink (CSI) selected
7	CS_IN7	R/W	0h	0h = Current Source (CSO) selected 1h = Current Sink (CSI) selected
6	CS_IN6	R/W	0h	0h = Current Source (CSO) selected 1h = Current Sink (CSI) selected
5	CS_IN5	R/W	0h	0h = Current Source (CSO) selected 1h = Current Sink (CSI) selected
4	CS_IN4	R/W	0h	0h = Current Source (CSO) selected 1h = Current Sink (CSI) selected
3	CS_IN3	R/W	0h	0h = Current Source (CSO) selected 1h = Current Sink (CSI) selected
2	CS_IN2	R/W	0h	0h = Current Source (CSO) selected 1h = Current Sink (CSI) selected
1	CS_IN1	R/W	0h	0h = Current Source (CSO) selected 1h = Current Sink (CSI) selected
0	CS_IN0	R/W	0h	0h = Current Source (CSO) selected 1h = Current Sink (CSI) selected

8.6.26 WC_CFG0 Register (Offset = 1Dh) [Reset = 0h]

WC_CFG0 is shown in Figure 8-49 and described in Table 8-37.

Return to Summary Table.

Figure 8-49 WC_CFG0 Register

23	22	21	20	19	18	17	16	15	14	13	12
WC_IN11			WC_IN10			WC_IN8_IN9			WC_IN6_IN7
R/W-0h			R/W-0h			R/W-0h			R/W-0h
11	10	9	8	7	6	5	4	3	2	1	0
WC_IN5			WC_IN4			WC_IN2_IN3			WC_IN0_IN1
R/W-0h			R/W-0h			R/W-0h			R/W-0h

LEGEND: R/W = Read/Write

Table 8-37 WC_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
23-21	WC_IN11	R/W	0h	0h = no wetting current 1h = 1 mA (typical) wetting current 2h = 2 mA (typical) wetting current 3h = 5 mA (typical) wetting current 4h = 10 mA (typical) wetting current 5h-7h = 15 mA (typical) wetting current
20-18	WC_IN10	R/W	0h	0h = no wetting current 1h = 1 mA (typical) wetting current 2h = 2 mA (typical) wetting current 3h = 5 mA (typical) wetting current 4h = 10 mA (typical) wetting current 5h-7h = 15 mA (typical) wetting current
17-15	WC_IN8_IN9	R/W	0h	0h = no wetting current 1h = 1 mA (typical) wetting current 2h = 2 mA (typical) wetting current 3h = 5 mA (typical) wetting current 4h = 10 mA (typical) wetting current 5h-7h = 15 mA (typical) wetting current
14-12	WC_IN6_IN7	R/W	0h	0h = no wetting current 1h = 1 mA (typical) wetting current 2h = 2 mA (typical) wetting current 3h = 5 mA (typical) wetting current 4h = 10 mA (typical) wetting current 5h-7h = 15 mA (typical) wetting current
11-9	WC_IN5	R/W	0h	0h = no wetting current 1h = 1 mA (typical) wetting current 2h = 2 mA (typical) wetting current 3h = 5 mA (typical) wetting current 4h = 10 mA (typical) wetting current 5h-7h = 15 mA (typical) wetting current
8-6	WC_IN4	R/W	0h	0h = no wetting current 1h = 1 mA (typical) wetting current 2h = 2 mA (typical) wetting current 3h = 5 mA (typical) wetting current 4h = 10 mA (typical) wetting current 5h-7h = 15 mA (typical) wetting current
5-3	WC_IN2_IN3	R/W	0h	0h = no wetting current 1h = 1 mA (typical) wetting current 2h = 2 mA (typical) wetting current 3h = 5 mA (typical) wetting current 4h = 10 mA (typical) wetting current 5h-7h = 15 mA (typical) wetting current
2-0	WC_IN0_IN1	R/W	0h	0h = no wetting current 1h = 1 mA (typical) wetting current 2h = 2 mA (typical) wetting current 3h = 5 mA (typical) wetting current 4h = 10 mA (typical) wetting current 5h-7h = 15 mA (typical) wetting current

8.6.27 WC_CFG1 Register (Offset = 1Eh) [Reset = 0h]

WC_CFG1 is shown in Figure 8-50 and described in Table 8-38.

Return to Summary Table.

Figure 8-50 WC_CFG1 Register

23	22	21	20	19	18	17	16	15	14	13	12
RESERVED	AUTO_SCALE_DIS_CSI	AUTO_SCALE_DIS_CSO	WC_IN23			WC_IN22			WC_IN20_IN21
R-0h	R/W-0h	R/W-0h	R/W-0h			R/W-0h			R/W-0h
11	10	9	8	7	6	5	4	3	2	1	0
WC_IN18_IN19			WC_IN16_IN17			WC_IN14_IN15			WC_IN12_IN13
R/W-0h			R/W-0h			R/W-0h			R/W-0h

LEGEND: R/W = Read/Write; R = Read only

Table 8-38 WC_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
23	RESERVED	R	0h	Reserved
22	AUTO_SCALE_DIS_CSI	R/W	0h	0h = Enable wetting current auto-scaling (to 2 mA) in continuous mode for 10 mA and 15 mA settings upon switch closure for all inputs enabled with CSI 1h = Disable wetting current auto-scaling (to 2 mA) in continuous mode for 10 mA and 15 mA settings upon switch closure for all inputs enabled with CS For detailed descriptions for the wetting current auto-scaling, refer to section Wetting Current Auto-Scaling.
21	AUTO_SCALE_DIS_CSO	R/W	0h	0h = Enable wetting current auto-scaling (to 2 mA) in continuous mode for 10 mA and 15 mA settings upon switch closure for all inputs enabled with CSO 1h = Disable wetting current auto-scaling (to 2 mA) in continuous mode for 10 mA and 15 mA settings upon switch closure for all inputs enabled with CSO For detailed descriptions for the wetting current auto-scaling, refer to section Wetting Current Auto-Scaling.
20-18	WC_IN23	R/W	0h	0h = no wetting current 1h = 1 mA (typical) wetting current 2h = 2 mA (typical) wetting current 3h = 5 mA (typical) wetting current 4h = 10 mA (typical) wetting current 5h-7h = 15 mA (typical) wetting current
17-15	WC_IN22	R/W	0h	0h = no wetting current 1h = 1 mA (typical) wetting current 2h = 2 mA (typical) wetting current 3h = 5 mA (typical) wetting current 4h = 10 mA (typical) wetting current 5h-7h = 15 mA (typical) wetting current
14-12	WC_IN20_IN21	R/W	0h	0h = no wetting current 1h = 1 mA (typical) wetting current 2h = 2 mA (typical) wetting current 3h = 5 mA (typical) wetting current 4h = 10 mA (typical) wetting current 5h-7h = 15 mA (typical) wetting current
11-9	WC_IN18_IN19	R/W	0h	0h = no wetting current 1h = 1 mA (typical) wetting current 2h = 2 mA (typical) wetting current 3h = 5 mA (typical) wetting current 4h = 10 mA (typical) wetting current 5h-7h = 15 mA (typical) wetting current
8-6	WC_IN16_IN17	R/W	0h	0h = no wetting current 1h = 1 mA (typical) wetting current 2h = 2 mA (typical) wetting current 3h = 5 mA (typical) wetting current 4h = 10 mA (typical) wetting current 5h-7h = 15 mA (typical) wetting current
5-3	WC_IN14_IN15	R/W	0h	0h = no wetting current 1h = 1 mA (typical) wetting current 2h = 2 mA (typical) wetting current 3h = 5 mA (typical) wetting current 4h = 10 mA (typical) wetting current 5h-7h = 15 mA (typical) wetting current
2-0	WC_IN12_IN13	R/W	0h	0h = no wetting current 1h = 1 mA (typical) wetting current 2h = 2 mA (typical) wetting current 3h = 5 mA (typical) wetting current 4h = 10 mA (typical) wetting current 5h-7h = 15 mA (typical) wetting current

8.6.28 CCP_CFG0 Register (Offset = 1Fh) [Reset = 0h]

CCP_CFG0 is shown in Figure 8-51 and described in Table 8-39.

Return to Summary Table.

Figure 8-51 CCP_CFG0 Register

23	22	21	20	19	18	17	16	15	14	13	12
RESERVED
R-0h
11	10	9	8	7	6	5	4	3	2	1	0
RESERVED					CCP_TIME			WC_CCP3	WC_CCP2	WC_CCP1	WC_CCP0
R-0h					R-0h			R-0h	R-0h	R-0h	R-0h

LEGEND: R/W = Read/Write; R = Read only

Table 8-39 CCP_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
23-7	RESERVED	R	0h	Reserved
6-4	CCP_TIME	R/W	0h	Wetting current activation time in CCP mode 0h = 64 μs 1h = 128 μs 2h = 192 μs 3h = 256 μs 4h = 320 μs 5h = 384 μs 6h = 448 μs 7h = 512 μs
3	WC_CCP3	R/W	0h	Wetting current setting for IN18 to IN23 in CCP mode 0h = 10 mA (typical) wetting current 1h = 15 mA (typical) wetting current
2	WC_CCP2	R/W	0h	Wetting current setting for IN12 to IN17 in CCP mode 0h = 10 mA (typical) wetting current 1h = 15 mA (typical) wetting current
1	WC_CCP1	R/W	0h	Wetting current setting for IN6 to IN11 in CCP mode 0h = 10 mA (typical) wetting current 1h = 15 mA (typical) wetting current
0	WC_CCP0	R/W	0h	Wetting current setting for IN0 to IN5 in CCP mode 0h = 10 mA (typical) wetting current 1h = 15 mA (typical) wetting current

8.6.29 CCP_CFG1 Register (Offset = 20h) [Reset = 0h]

CCP_CFG1 is shown in Figure 8-52 and described in Table 8-40.

Return to Summary Table.

Figure 8-52 CCP_CFG1 Register

23	22	21	20	19	18	17	16
CCP_IN23	CCP_IN22	CCP_IN21	CCP_IN20	CCP_IN19	CCP_IN18	CCP_IN17	CCP_IN16
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

15	14	13	12	11	10	9	8
CCP_IN15	CCP_IN14	CCP_IN13	CCP_IN12	CCP_IN11	CCP_IN10	CCP_IN9	CCP_IN8
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

7	6	5	4	3	2	1	0
CCP_IN7	CCP_IN6	CCP_IN5	CCP_IN4	CCP_IN3	CCP_IN2	CCP_IN1	CCP_IN0
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

LEGEND: R/W = Read/Write

Table 8-40 CCP_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
23	CCP_IN23	R/W	0h	0h = no CCP wetting current 1h = CCP wetting current activated
22	CCP_IN22	R/W	0h	0h = no CCP wetting current 1h = CCP wetting current activated
21	CCP_IN21	R/W	0h	0h = no CCP wetting current 1h = CCP wetting current activated
20	CCP_IN20	R/W	0h	0h = no CCP wetting current 1h = CCP wetting current activated
19	CCP_IN19	R/W	0h	0h = no CCP wetting current 1h = CCP wetting current activated
18	CCP_IN18	R/W	0h	0h = no CCP wetting current 1h = CCP wetting current activated
17	CCP_IN17	R/W	0h	0h = no CCP wetting current 1h = CCP wetting current activated
16	CCP_IN16	R/W	0h	0h = no CCP wetting current 1h = CCP wetting current activated
15	CCP_IN15	R/W	0h	0h = no CCP wetting current 1h = CCP wetting current activated
14	CCP_IN14	R/W	0h	0h = no CCP wetting current 1h = CCP wetting current activated
13	CCP_IN13	R/W	0h	0h = no CCP wetting current 1h = CCP wetting current activated
12	CCP_IN12	R/W	0h	0h = no CCP wetting current 1h = CCP wetting current activated
11	CCP_IN11	R/W	0h	0h = no CCP wetting current 1h = CCP wetting current activated
10	CCP_IN10	R/W	0h	0h = no CCP wetting current 1h = CCP wetting current activated
9	CCP_IN9	R/W	0h	0h = no CCP wetting current 1h = CCP wetting current activated
8	CCP_IN8	R/W	0h	0h = no CCP wetting current 1h = CCP wetting current activated
7	CCP_IN7	R/W	0h	0h = no CCP wetting current 1h = CCP wetting current activated
6	CCP_IN6	R/W	0h	0h = no CCP wetting current 1h = CCP wetting current activated
5	CCP_IN5	R/W	0h	0h = no CCP wetting current 1h = CCP wetting current activated
4	CCP_IN4	R/W	0h	0h = no CCP wetting current 1h = CCP wetting current activated
3	CCP_IN3	R/W	0h	0h = no CCP wetting current 1h = CCP wetting current activated
2	CCP_IN2	R/W	0h	0h = no CCP wetting current 1h = CCP wetting current activated
1	CCP_IN1	R/W	0h	0h = no CCP wetting current 1h = CCP wetting current activated
0	CCP_IN0	R/W	0h	0h = no CCP wetting current 1h = CCP wetting current activated

8.6.30 THRES_COMP Register (Offset = 21h) [Reset = 0h]

THRES_COMP is shown in Figure 8-53 and described in Table 8-41.

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Figure 8-53 THRES_COMP Register

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED				THRES_COMP_IN20_IN23		THRES_COMP_IN16_IN19
R-0h				R/W-0h		R/W-0h

7	6	5	4	3	2	1	0
THRES_COMP_IN12_IN15		THRES_COMP_IN8_IN11		THRES_COMP_IN4_IN7		THRES_COMP_IN0_IN3
R/W-0h		R/W-0h		R/W-0h		R/W-0h

LEGEND: R/W = Read/Write; R = Read only

Table 8-41 THRES_COMP Register Field Descriptions

Bit	Field	Type	Reset	Description
23-12	RESERVED	R	0h	Reserved
11-10	THRES_COMP_IN20_IN23	R/W	0h	These 2 bits configure the comparator thresholds for input channels IN20 to IN23. 0h = comparator threshold set to 2 V 1h = comparator threshold set to 2.7 V 2h = comparator threshold set to 3 V 3h = comparator threshold set to 4 V
9-8	THRES_COMP_IN16_IN19	R/W	0h	These 2 bits configure the comparator thresholds for input channels IN16 to IN19. 0h = comparator threshold set to 2 V 1h = comparator threshold set to 2.7 V 2h = comparator threshold set to 3 V 3h = comparator threshold set to 4 V
7-6	THRES_COMP_IN12_IN15	R/W	0h	These 2 bits configure the comparator thresholds for input channels IN12 to IN15. 0h = comparator threshold set to 2 V 1h = comparator threshold set to 2.7 V 2h = comparator threshold set to 3 V 3h = comparator threshold set to 4 V
5-4	THRES_COMP_IN8_IN11	R/W	0h	These 2 bits configure the comparator thresholds for input channels IN8 to IN11. 0h = comparator threshold set to 2 V 1h = comparator threshold set to 2.7 V 2h = comparator threshold set to 3 V 3h = comparator threshold set to 4 V
3-2	THRES_COMP_IN4_IN7	R/W	0h	These 2 bits configure the comparator thresholds for input channels IN4 to IN7 0h = comparator threshold set to 2 V 1h = comparator threshold set to 2.7 V 2h = comparator threshold set to 3 V 3h = comparator threshold set to 4 V
1-0	THRES_COMP_IN0_IN3	R/W	0h	These 2 bits configure the comparator thresholds for input channels IN0 to IN3 0h = comparator threshold set to 2 V 1h = comparator threshold set to 2.7 V 2h = comparator threshold set to 3 V 3h = comparator threshold set to 4 V

8.6.31 INT_EN_COMP1 Register (Offset = 22h) [Reset = 0h]

INT_EN_COMP1 is shown in Figure 8-54 and described in Table 8-42.

Return to Summary Table.

Figure 8-54 INT_EN_COMP1 Register

23	22	21	20	19	18	17	16	15	14	13	12
INC_EN_11		INC_EN_10		INC_EN_9		INC_EN_8		INC_EN_7		INC_EN_6
R/W-0h		R/W-0h		R/W-0h		R/W-0h		R/W-0h		R/W-0h
11	10	9	8	7	6	5	4	3	2	1	0
INC_EN_5		INC_EN_4		INC_EN_3		INC_EN_2		INC_EN_1		INC_EN_0
R/W-0h		R/W-0h		R/W-0h		R/W-0h		R/W-0h		R/W-0h

LEGEND: R/W = Read/Write

Table 8-42 INT_EN_COMP1 Register Field Descriptions

Bit	Field	Type	Reset	Description
23-22	INC_EN_11	R/W	0h	0h = no interrupt generation for IN11. 1h = interrupt generation on rising edge above THRES_COMP_IN8_IN11 for IN11. 2h = interrupt generation on falling edge below THRES_COMP_IN8_IN11 for IN11. 3h = interrupt generation on falling and rising edge of THRES_COMP_IN8_IN11 for IN11.
21-20	INC_EN_10	R/W	0h	0h = no interrupt generation for IN10 1h = interrupt generation on rising edge above THRES_COMP_IN8_IN11 for IN10. 2h = interrupt generation on falling edge below THRES_COMP_IN8_IN11 for IN10. 3h = interrupt generation on falling and rising edge of THRES_COMP_IN8_IN11 for IN10.
19-18	INC_EN_9	R/W	0h	0h = no interrupt generation for IN9. 1h = interrupt generation on rising edge above THRES_COMP_IN8_IN11 for IN9. 2h = interrupt generation on falling edge below THRES_COMP_IN8_IN11 for IN9. 3h = interrupt generation on falling and rising edge of THRES_COMP_IN8_IN11 for IN9.
17-16	INC_EN_8	R/W	0h	0h = no interrupt generation for IN8. 1h = interrupt generation on rising edge above THRES_COMP_IN8_IN11 for IN8. 2h = interrupt generation on falling edge below THRES_COMP_IN8_IN11 for IN8. 3h = interrupt generation on falling and rising edge of THRES_COMP_IN8_IN11 for IN8.
15-14	INC_EN_7	R/W	0h	0h = no interrupt generation for IN7. 1h = interrupt generation on rising edge above THRES_COMP_IN4_IN7 for IN7. 2h = interrupt generation on falling edge below THRES_COMP_IN4_IN7 for IN7. 3h = interrupt generation on falling and rising edge of THRES_COMP_IN4_IN7 for IN7.
13-12	INC_EN_6	R/W	0h	0h = no interrupt generation for IN6. 1h = interrupt generation on rising edge above THRES_COMP_IN4_IN7 for IN6. 2h = interrupt generation on falling edge below THRES_COMP_IN4_IN7 for IN6. 3h = interrupt generation on falling and rising edge of THRES_COMP_IN4_IN7 for IN6.
11-10	INC_EN_5	R/W	0h	0h = no interrupt generation for IN5. 1h = interrupt generation on rising edge above THRES_COMP_IN4_IN7 for IN5. 2h = interrupt generation on falling edge below THRES_COMP_IN4_IN7 for IN5. 3h = interrupt generation on falling and rising edge of THRES_COMP_IN4_IN7 for IN5.
9-8	INC_EN_4	R/W	0h	0h = no interrupt generation for IN4. 1h = interrupt generation on rising edge above THRES_COMP_IN4_IN7 for IN4. 2h = interrupt generation on falling edge below THRES_COMP_IN4_IN7 for IN4. 3h = interrupt generation on falling and rising edge of THRES_COMP_IN4_IN7 for IN4.
7-6	INC_EN_3	R/W	0h	0h = no interrupt generation for IN3. 1h = interrupt generation on rising edge above THRES_COMP_IN0_IN3 for IN3. 2h = interrupt generation on falling edge below THRES_COMP_IN0_IN3 for IN3. 3h = interrupt generation on falling and rising edge of THRES_COMP_IN0_IN3 for IN3.
5-4	INC_EN_2	R/W	0h	0h = no interrupt generation for IN2. 1h = interrupt generation on rising edge above THRES_COMP_IN0_IN3 for IN2. 2h = interrupt generation on falling edge below THRES_COMP_IN0_IN3 for IN2. 3h = interrupt generation on falling and rising edge of THRES_COMP_IN0_IN3 for IN2.
3-2	INC_EN_1	R/W	0h	0h = no interrupt generation for IN1. 1h = interrupt generation on rising edge above THRES_COMP_IN0_IN3 for IN1. 2h = interrupt generation on falling edge below THRES_COMP_IN0_IN3 for IN1. 3h = interrupt generation on falling and rising edge of THRES_COMP_IN0_IN3 for IN1.
1-0	INC_EN_0	R/W	0h	0h = no interrupt generation for IN0. 1h = interrupt generation on rising edge above THRES_COMP_IN0_IN3 for IN0. 2h = interrupt generation on falling edge below THRES_COMP_IN0_IN3 for IN0. 3h = interrupt generation on falling and rising edge of THRES_COMP_IN0_IN3 for IN0.

8.6.32 INT_EN_COMP2 Register (Offset = 23h) [Reset = 0h]

INT_EN_COMP2 is shown in Figure 8-55 and described in Table 8-43.

Return to Summary Table.

Figure 8-55 INT_EN_COMP2 Register

23	22	21	20	19	18	17	16	15	14	13	12
INC_EN_23		INC_EN_22		INC_EN_21		INC_EN_20		INC_EN_19		INC_EN_18
R/W-0h		R/W-0h		R/W-0h		R/W-0h		R/W-0h		R/W-0h
11	10	9	8	7	6	5	4	3	2	1	0
INC_EN_17		INC_EN_16		INC_EN_15		INC_EN_14		INC_EN_13		INC_EN_12
R/W-0h		R/W-0h		R/W-0h		R/W-0h		R/W-0h		R/W-0h

LEGEND: R/W = Read/Write

Table 8-43 INT_EN_COMP2 Register Field Descriptions

Bit	Field	Type	Reset	Description
23-22	INC_EN_23	R/W	0h	0h = no interrupt generation for IN23. 1h = interrupt generation on rising edge above THRES_COMP_IN20_IN23 for IN23. 2h = interrupt generation on falling edge below THRES_COMP_IN20_IN23 for IN23. 3h = interrupt generation on falling and rising edge of THRES_COMP_IN20_IN23 for IN23.
21-20	INC_EN_22	R/W	0h	0h = no interrupt generation for IN22. 1h = interrupt generation on rising edge above THRES_COMP_IN20_IN23 for IN22. 2h = interrupt generation on falling edge below THRES_COMP_IN20_IN23 for IN22. 3h = interrupt generation on falling and rising edge of THRES_COMP_IN20_IN23 for IN22.
19-18	INC_EN_21	R/W	0h	0h = no interrupt generation for IN21. 1h = interrupt generation on rising edge above THRES_COMP_IN20_IN23 for IN21. 2h = interrupt generation on falling edge below THRES_COMP_IN20_IN23 for IN21. 3h = interrupt generation on falling and rising edge of THRES_COMP_IN20_IN23 for IN21.
17-16	INC_EN_20	R/W	0h	0h = no interrupt generation for IN20. 1h = interrupt generation on rising edge above THRES_COMP_IN20_IN23 for IN20. 2h = interrupt generation on falling edge below THRES_COMP_IN20_IN23 for IN20. 3h = interrupt generation on falling and rising edge of THRES_COMP_IN20_IN23 for IN20.
15-14	INC_EN_19	R/W	0h	0h = no interrupt generation for IN19. 1h = interrupt generation on rising edge above THRES_COMP_IN16_IN19 for IN19. 2h = interrupt generation on falling edge below THRES_COMP_IN16_IN19 for IN19. 3h = interrupt generation on falling and rising edge of THRES_COMP_IN16_IN19 for IN19.
13-12	INC_EN_18	R/W	0h	0h = no interrupt generation for IN18. 1h = interrupt generation on rising edge above THRES_COMP_IN16_IN19 for IN18. 2h = interrupt generation on falling edge below THRES_COMP_IN16_IN19 for IN18. 3h = interrupt generation on falling and rising edge of THRES_COMP_IN16_IN19 for IN18.
11-10	INC_EN_17	R/W	0h	0h = no interrupt generation for IN17. 1h = interrupt generation on rising edge above THRES_COMP_IN16_IN19 for IN17. 2h = interrupt generation on falling edge below THRES_COMP_IN16_IN19 for IN17. 3h = interrupt generation on falling and rising edge of THRES_COMP_IN16_IN19 for IN17.
9-8	INC_EN_16	R/W	0h	0h = no interrupt generation for IN16. 1h = interrupt generation on rising edge above THRES_COMP_IN16_IN19 for IN16. 2h = interrupt generation on falling edge below THRES_COMP_IN16_IN19 for IN16. 3h = interrupt generation on falling and rising edge of THRES_COMP_IN16_IN19 for IN16.
7-6	INC_EN_15	R/W	0h	0h = no interrupt generation for IN15. 1h = interrupt generation on rising edge above THRES_COMP_IN12_IN15 for IN15. 2h = interrupt generation on falling edge below THRES_COMP_IN12_IN15 for IN15. 3h = interrupt generation on falling and rising edge of THRES_COMP_IN12_IN15 for IN15.
5-4	INC_EN_14	R/W	0h	0h = no interrupt generation for IN14. 1h = interrupt generation on rising edge above THRES_COMP_IN12_IN15 for IN14. 2h = interrupt generation on falling edge below THRES_COMP_IN12_IN15 for IN14. 3h = interrupt generation on falling and rising edge of THRES_COMP_IN12_IN15 for IN14.
3-2	INC_EN_13	R/W	0h	0h = no interrupt generation for IN13. 1h = interrupt generation on rising edge above THRES_COMP_IN12_IN15 for IN13. 2h = interrupt generation on falling edge below THRES_COMP_IN12_IN15 for IN13. 3h = interrupt generation on falling and rising edge of THRES_COMP_IN12_IN15 for IN13.
1-0	INC_EN_12	R/W	0h	0h = no interrupt generation for IN12. 1h = interrupt generation on rising edge above THRES_COMP_IN12_IN15 for IN12. 2h = interrupt generation on falling edge below THRES_COMP_IN12_IN15 for IN12. 3h = interrupt generation on falling and rising edge of THRES_COMP_IN12_IN15 for IN12.

8.6.33 INT_EN_CFG0 Register (Offset = 24h) [Reset = 0h]

INT_EN_CFG0 is shown in Figure 8-56 and described in Table 8-44.

Return to Summary Table.

Figure 8-56 INT_EN_CFG0 Register

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED				ADC_DIAG_EN	WET_DIAG_EN	VS1_EN	VS0_EN
R-0h				R/W-0h	R/W-0h	R/W-0h	R/W-0h

7	6	5	4	3	2	1	0
CRC_CALC_EN	UV_EN	OV_EN	TW_EN	TSD_EN	SSC_EN	PRTY_FAIL_EN	SPI_FAIL_EN
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

LEGEND: R/W = Read/Write; R = Read only

Table 8-44 INT_EN_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
23-12	RESERVED	R	0h	Reserved
11	ADC_DIAG_EN	R/W	0h	0h = INT pin assertion due to ADC error disabled. 1h = INT pin assertion due to ADC error enabled.
10	WET_DIAG_EN	R/W	0h	0h = INT pin assertion due to wetting current error disabled. 1h = INT pin assertion due to wetting current error enabled.
9	VS1_EN	R/W	0h	0h = INT pin assertion due to VS1 threshold crossing disabled. 1h = INT pin assertion due to VS1 threshold crossing enabled.
8	VS0_EN	R/W	0h	0h = INT pin assertion due to VS0 threshold crossing disabled. 1h = INT pin assertion due to VS0 threshold crossing enabled.
7	CRC_CALC_EN	R/W	0h	0h = INT pin assertion due to CRC calculation completion disabled. 1h = INT pin assertion due to CRC calculation completion enabled.
6	UV_EN	R/W	0h	0h = INT pin assertion due to UV event disabled. 1h = INT pin assertion due to UV event enabled.
5	OV_EN	R/W	0h	0h = INT pin assertion due to OV event disabled. 1h = INT pin assertion due to OV event enabled.
4	TW_EN	R/W	0h	0h = INT pin assertion due to TW event disabled. 1h = INT pin assertion due to TW event enabled.
3	TSD_EN	R/W	0h	0h = INT pin assertion due to TSD event disabled. 1h = INT pin assertion due to TSD event enabled.
2	SSC_EN	R/W	0h	0h = INT pin assertion due to SSC event disabled. 1h = INT pin assertion due to SSC event enabled.
1	PRTY_FAIL_EN	R/W	0h	0h = INT pin assertion due to parity fail event disabled. 1h = INT pin assertion due to parity fail event enabled.
0	SPI_FAIL_EN	R/W	0h	0h = INT pin assertion due to SPI fail event disabled. 1h = INT pin assertion due to SPI fail event enabled.

8.6.34 INT_EN_CFG1 Register (Offset = 25h) [Reset = 0h]

INT_EN_CFG1 is shown in Figure 8-57 and described in Table 8-45.

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Figure 8-57 INT_EN_CFG1 Register

23	22	21	20	19	18	17	16	15	14	13	12
IN11_EN		IN10_EN		IN9_EN		IN8_EN		IN7_EN		IN6_EN
R/W-0h		R/W-0h		R/W-0h		R/W-0h		R/W-0h		R/W-0h
11	10	9	8	7	6	5	4	3	2	1	0
IN5_EN		IN4_EN		IN3_EN		IN2_EN		IN1_EN		IN0_EN
R/W-0h		R/W-0h		R/W-0h		R/W-0h		R/W-0h		R/W-0h

LEGEND: R/W = Read/Write

Table 8-45 INT_EN_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
23-22	IN11_EN	R/W	0h	0h = no interrupt generation for IN11. 1h = interrupt generation on rising edge above THRESx for IN11. 2h = interrupt generation on falling edge below THRESx for IN11. 3h = interrupt generation on falling and rising edge of THRESx for IN11.
21-20	IN10_EN	R/W	0h	0h = no interrupt generation for IN10. 1h = interrupt generation on rising edge above THRESx for IN10. 2h = interrupt generation on falling edge below THRESx for IN10. 3h = interrupt generation on falling and rising edge of THRESx for IN10.
19-18	IN9_EN	R/W	0h	0h = no interrupt generation for IN9. 1h = interrupt generation on rising edge above THRESx for IN9. 2h = interrupt generation on falling edge below THRESx for IN9. 3h = interrupt generation on falling and rising edge of THRESx for IN9.
17-16	IN8_EN	R/W	0h	0h = no interrupt generation for IN8. 1h = interrupt generation on rising edge above THRESx for IN8. 2h = interrupt generation on falling edge below THRESx for IN8. 3h = interrupt generation on falling and rising edge of THRESx for IN8.
15-14	IN7_EN	R/W	0h	0h = no interrupt generation for IN7. 1h = interrupt generation on rising edge above THRESx for IN7. 2h = interrupt generation on falling edge below THRESx for IN7. 3h = interrupt generation on falling and rising edge of THRESx for IN7.
13-12	IN6_EN	R/W	0h	0h = no interrupt generation for IN6. 1h = interrupt generation on rising edge above THRESx for IN6. 2h = interrupt generation on falling edge below THRESx for IN6. 3h = interrupt generation on falling and rising edge of THRESx for IN6.
11-10	IN5_EN	R/W	0h	0h = no interrupt generation for IN5. 1h = interrupt generation on rising edge above THRESx for IN5. 2h = interrupt generation on falling edge below THRESx for IN5. 3h = interrupt generation on falling and rising edge of THRESx for IN5.
9-8	IN4_EN	R/W	0h	0h = no interrupt generation for IN4. 1h = interrupt generation on rising edge above THRESx for IN4. 2h = interrupt generation on falling edge below THRESx for IN4. 3h = interrupt generation on falling and rising edge of THRESx for IN4.
7-6	IN3_EN	R/W	0h	0h = no interrupt generation for IN3. 1h = interrupt generation on rising edge above THRESx for IN3. 2h = interrupt generation on falling edge below THRESx for IN3. 3h = interrupt generation on falling and rising edge of THRESx for IN3.
5-4	IN2_EN	R/W	0h	0h = no interrupt generation for IN2. 1h = interrupt generation on rising edge above THRESx for IN2. 2h = interrupt generation on falling edge below THRESx for IN2. 3h = interrupt generation on falling and rising edge of THRESx for IN2.
3-2	IN1_EN	R/W	0h	0h = no interrupt generation for IN1. 1h = interrupt generation on rising edge above THRESx for IN1. 2h = interrupt generation on falling edge below THRESx for IN1. 3h = interrupt generation on falling and rising edge of THRESx for IN1.
1-0	IN0_EN	R/W	0h	0h = no interrupt generation for IN0. 1h = interrupt generation on rising edge above THRESx for IN0. 2h = interrupt generation on falling edge below THRESx for IN0. 3h = interrupt generation on falling and rising edge of THRESx for IN0.

8.6.35 INT_EN_CFG2 Register (Offset = 26h) [Reset = 0h]

INT_EN_CFG2 is shown in Figure 8-58 and described in Table 8-46.

Return to Summary Table.

Figure 8-58 INT_EN_CFG2 Register

23	22	21	20	19	18	17	16	15	14	13	12
IN17_EN				IN16_EN				IN15_EN
R/W-0h				R/W-0h				R/W-0h
11	10	9	8	7	6	5	4	3	2	1	0
IN14_EN				IN13_EN				IN12_EN
R/W-0h				R/W-0h				R/W-0h

LEGEND: R/W = Read/Write

Table 8-46 INT_EN_CFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
23-20	IN17_EN	R/W	0h	xx00: no interrupt generation for IN17 w.r.t. THRES2A. xx01: interrupt generation on rising edge above THRES2A for IN17. xx10: interrupt generation on falling edge below THRES2A for IN17. xx11: interrupt generation on falling and rising edge of THRES2A for IN17. 00xx: no interrupt generation for IN17 w.r.t. THRES2B. 01xx: interrupt generation on rising edge above THRES2B for IN17. 10xx: interrupt generation on falling edge below THRES2B for IN17. 11xx: interrupt generation on falling and rising edge of THRES2B for IN17.
19-16	IN16_EN	R/W	0h	xx00: no interrupt generation for IN16 w.r.t. THRES2A. xx01: interrupt generation on rising edge above THRES2A for IN16. xx10: interrupt generation on falling edge below THRES2A for IN16. xx11: interrupt generation on falling and rising edge of THRES2A for IN16. 00xx: no interrupt generation for IN16 w.r.t. THRES2B. 01xx: interrupt generation on rising edge above THRES2B for IN16. 10xx: interrupt generation on falling edge below THRES2B for IN16. 11xx: interrupt generation on falling and rising edge of THRES2B for IN16.
15-12	IN15_EN	R/W	0h	xx00: no interrupt generation for IN15 w.r.t. THRES2A. xx01: interrupt generation on rising edge above THRES2A for IN15. xx10: interrupt generation on falling edge below THRES2A for IN15. xx11: interrupt generation on falling and rising edge of THRES2A for IN15. 00xx: no interrupt generation for IN15 w.r.t. THRES2B. 01xx: interrupt generation on rising edge above THRES2B for IN15. 10xx: interrupt generation on falling edge below THRES2B for IN15. 11xx: interrupt generation on falling and rising edge of THRES2B for IN15.
11-8	IN14_EN	R/W	0h	xx00: no interrupt generation for IN14 w.r.t. THRES2A. xx01: interrupt generation on rising edge above THRES2A for IN14. xx10: interrupt generation on falling edge below THRES2A for IN14. xx11: interrupt generation on falling and rising edge of THRES2A for IN14. 00xx: no interrupt generation for IN14 w.r.t. THRES2B. 01xx: interrupt generation on rising edge above THRES2B for IN14. 10xx: interrupt generation on falling edge below THRES2B for IN14. 11xx: interrupt generation on falling and rising edge of THRES2B for IN14.
7-4	IN13_EN	R/W	0h	xx00: no interrupt generation for IN13 w.r.t. THRES2A. xx01: interrupt generation on rising edge above THRES2A for IN13. xx10: interrupt generation on falling edge below THRES2A for IN13. xx11: interrupt generation on falling and rising edge of THRES2A for IN13. 00xx: no interrupt generation for IN13 w.r.t. THRES2B. 01xx: interrupt generation on rising edge above THRES2B for IN13. 10xx: interrupt generation on falling edge below THRES2B for IN13. 11xx: interrupt generation on falling and rising edge of THRES2B for IN13.
3-0	IN12_EN	R/W	0h	xx00: no interrupt generation for IN12 w.r.t. THRES2A. xx01: interrupt generation on rising edge above THRES2A for IN12. xx10: interrupt generation on falling edge below THRES2A for IN12. xx11: interrupt generation on falling and rising edge of THRES2A for IN12. 00xx: no interrupt generation for IN12 w.r.t. THRES2B. 01xx: interrupt generation on rising edge above THRES2B for IN12. 10xx: interrupt generation on falling edge below THRES2B for IN12. 11xx: interrupt generation on falling and rising edge of THRES2B for IN12.

8.6.36 INT_EN_CFG3 Register (Offset = 27h) [Reset = 0h]

INT_EN_CFG3 is shown in Figure 8-59 and described in Table 8-47.

Return to Summary Table.

Figure 8-59 INT_EN_CFG3 Register

23	22	21	20	19	18	17	16	15	14	13	12
IN21_EN						IN20_EN
R/W-0h						R/W-0h
11	10	9	8	7	6	5	4	3	2	1	0
IN19_EN						IN18_EN
R/W-0h						R/W-0h

LEGEND: R/W = Read/Write

Table 8-47 INT_EN_CFG3 Register Field Descriptions

Bit	Field	Type	Reset	Description
23-18	IN21_EN	R/W	0h	xxxx00: no interrupt generation for IN21 w.r.t. THRES3A xxxx01: interrupt generation on rising edge above THRES3A for IN21 xxxx10: interrupt generation on falling edge below THRES3A for IN21 xxxx11: interrupt generation on falling and rising edge of THRES3A for IN21 xx00xx: no interrupt generation for IN21 w.r.t. THRES3B xx01xx: interrupt generation on rising edge above THRES3B for IN21 xx10xx: interrupt generation on falling edge below THRES3B for IN21 xx11xx: interrupt generation on falling and rising edge of THRES3B for IN21 00xxxx: no interrupt generation for IN21 w.r.t. THRES3C 01xxxx: interrupt generation on rising edge above THRES3C for IN21 10xxxx: interrupt generation on falling edge below THRES3C for IN21 11xxxx: interrupt generation on falling and rising edge of THRES3C for IN21
17-12	IN20_EN	R/W	0h	xxxx00: no interrupt generation for IN20 w.r.t. THRES3A xxxx01: interrupt generation on rising edge above THRES3A for IN20 xxxx10: interrupt generation on falling edge below THRES3A for IN20 xxxx11: interrupt generation on falling and rising edge of THRES3A for IN20 xx00xx: no interrupt generation for IN20 w.r.t. THRES3B xx01xx: interrupt generation on rising edge above THRES3B for IN20 xx10xx: interrupt generation on falling edge below THRES3B for IN20 xx11xx: interrupt generation on falling and rising edge of THRES3B for IN20 00xxxx: no interrupt generation for IN20 w.r.t. THRES3C 01xxxx: interrupt generation on rising edge above THRES3C for IN20 10xxxx: interrupt generation on falling edge below THRES3C for IN20 11xxxx: interrupt generation on falling and rising edge of THRES3C for IN20
11-6	IN19_EN	R/W	0h	xxxx00: no interrupt generation for IN19 w.r.t. THRES3A xxxx01: interrupt generation on rising edge above THRES3A for IN19 xxxx10: interrupt generation on falling edge below THRES3A for IN19 xxxx11: interrupt generation on falling and rising edge of THRES3A for IN19 xx00xx: no interrupt generation for IN19 w.r.t. THRES3B xx01xx: interrupt generation on rising edge above THRES3B for IN19 xx10xx: interrupt generation on falling edge below THRES3B for IN19 xx11xx: interrupt generation on falling and rising edge of THRES3B for IN19 00xxxx: no interrupt generation for IN19 w.r.t. THRES3C 01xxxx: interrupt generation on rising edge above THRES3C for IN19 10xxxx: interrupt generation on falling edge below THRES3C for IN19 11xxxx: interrupt generation on falling and rising edge of THRES3C for IN19
5-0	IN18_EN	R/W	0h	xxxx00: no interrupt generation for IN18 w.r.t. THRES3A xxxx01: interrupt generation on rising edge above THRES3A for IN18 xxxx10: interrupt generation on falling edge below THRES3A for IN18 xxxx11: interrupt generation on falling and rising edge of THRES3A for IN18 xx00xx: no interrupt generation for IN18 w.r.t. THRES3B xx01xx: interrupt generation on rising edge above THRES3B for IN18 xx10xx: interrupt generation on falling edge below THRES3B for IN18 xx11xx: interrupt generation on falling and rising edge of THRES3B for IN18 00xxxx: no interrupt generation for IN18 w.r.t. THRES3C 01xxxx: interrupt generation on rising edge above THRES3C for IN18 10xxxx: interrupt generation on falling edge below THRES3C for IN18 11xxxx: interrupt generation on falling and rising edge of THRES3C for IN18

8.6.37 INT_EN_CFG4 Register (Offset = 28h) [Reset = 0h]

INT_EN_CFG4 is shown in Figure 8-60 and described in Table 8-48.

Return to Summary Table.

Figure 8-60 INT_EN_CFG4 Register

23	22	21	20	19	18	17	16	15	14	13	12
VS_TH1_EN				VS_TH0_EN				IN23_EN
R/W-0h				R/W-0h				R/W-0h
11	10	9	8	7	6	5	4	3	2	1	0
IN23_EN						IN22_EN
R/W-0h						R/W-0h

LEGEND: R/W = Read/Write

Table 8-48 INT_EN_CFG4 Register Field Descriptions

Bit	Field	Type	Reset	Description
23-20	VS_TH1_EN	R/W	0h	xx00: no interrupt generation for V_S w.r.t. VS1_THRES2A. xx01: interrupt generation on rising edge above VS1_THRES2A for V_S. xx10: interrupt generation on falling edge below VS1_THRES2A for V_S. xx11: interrupt generation on falling and rising edge of VS1_THRES2A for V_S. 00xx: no interrupt generation for V_S w.r.t. VS1_THRES2B. 01xx: interrupt generation on rising edge above VS1_THRES2B for V_S. 10xx: interrupt generation on falling edge below VS1_THRES2B for V_S. 11xx: interrupt generation on falling and rising edge of VS1_THRES2B for V_S.
19-16	VS_TH0_EN	R/W	0h	xx00: no interrupt generation for V_S w.r.t. VS0_THRES2A. xx01: interrupt generation on rising edge above VS0_THRES2A for V_S. xx10: interrupt generation on falling edge below VS0_THRES2A for V_S. xx11: interrupt generation on falling and rising edge of VS0_THRES2A for VS. 00xx: no interrupt generation for V_S w.r.t. VS0_THRES2B. 01xx: interrupt generation on rising edge above VS0_THRES2B for V_S. 10xx: interrupt generation on falling edge below VS0_THRES2B for V_S. 11xx: interrupt generation on falling and rising edge of VS0_THRES2B for V_S.
15-6	IN23_EN	R/W	0h	xxxxxxxx00: no interrupt generation for IN23 w.r.t. THRES3A. xxxxxxxx01: interrupt generation on rising edge above THRES3A for IN23. xxxxxxxx10: interrupt generation on falling edge below THRES3A for IN23. xxxxxxxx11: interrupt generation on falling and rising edge of THRES3A for IN23. xxxxxx00xx: no interrupt generation for IN23 w.r.t. THRES3B. xxxxxx01xx: interrupt generation on rising edge above THRES3B for IN23. xxxxxx10xx: interrupt generation on falling edge below THRES3B for IN23. xxxxxx11xx: interrupt generation on falling and rising edge of THRES3B for IN23. xxxx00xxxx: no interrupt generation for IN23 w.r.t. THRES3C. xxxx01xxxx: interrupt generation on rising edge above THRES3C for IN23. xxxx10xxxx: interrupt generation on falling edge below THRES3C for IN23. xxxx11xxxx: interrupt generation on falling and rising edge of THRES3C for IN23. xx00xxxxxx: no interrupt generation for IN23 w.r.t. THRES8. xx01xxxxxx: interrupt generation on rising edge above THRES8 for IN23. xx10xxxxxx: interrupt generation on falling edge below THRES8 for IN23. xx11xxxxxx: interrupt generation on falling and rising edge of THRES8 for IN23. 00xxxxxxxx: no interrupt generation for IN23 w.r.t. THRES9. 01xxxxxxxx: interrupt generation on rising edge above THRES9 for IN23. 10xxxxxxxx: interrupt generation on falling edge below THRES9 for IN23. 11xxxxxxxx: interrupt generation on falling and rising edge of THRES9 for IN23.
5-0	IN22_EN	R/W	0h	xxxx00: no interrupt generation for IN22 w.r.t. THRES3A. xxxx01: interrupt generation on rising edge above THRES3A for IN22. xxxx10: interrupt generation on falling edge below THRES3A for IN22. xxxx11: interrupt generation on falling and rising edge of THRES3A for IN22. xx00xx: no interrupt generation for IN22 w.r.t. THRES3B. xx01xx: interrupt generation on rising edge above THRES3B for IN22. xx10xx: interrupt generation on falling edge below THRES3B for IN22. xx11xx: interrupt generation on falling and rising edge of THRES3B for IN22. 00xxxx: no interrupt generation for IN22 w.r.t. THRES3C. 01xxxx: interrupt generation on rising edge above THRES3C for IN22. 10xxxx: interrupt generation on falling edge below THRES3C for IN22. 11xxxx: interrupt generation on falling and rising edge of THRES3C for IN22.

8.6.38 THRES_CFG0 Register (Offset = 29h) [Reset = 0h]

THRES_CFG0 is shown in Figure 8-61 and described in Table 8-49.

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Figure 8-61 THRES_CFG0 Register

23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED				THRES1										THRES0
R-0h				R-0h										R-0h

LEGEND: R/W = Read/Write; R = Read only

Table 8-49 THRES_CFG0 Register Field Descriptions

Bit

Field

Type

Reset

Description

23-20

RESERVED

Reserved

19-10

THRES1

R/W

10-bits value of threshold 1:

Bit10: LSB

Bit19: MSB

9-0

THRES0

R/W

10-bits value of threshold 0

Bit0: LSB

Bit9: MSB

8.6.39 THRES_CFG1 Register (Offset = 2Ah) [Reset = 0h]

THRES_CFG1 is shown in Figure 8-62 and described in Table 8-50.

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Figure 8-62 THRES_CFG1 Register

23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED				THRES3										THRES2
R-0h				R-0h										R-0h

LEGEND: R/W = Read/Write; R = Read only

Table 8-50 THRES_CFG1 Register Field Descriptions

Bit

Field

Type

Reset

Description

23-20

RESERVED

Reserved

19-10

THRES3

R/W

10-bits value of threshold 3:

Bit10: LSB

Bit19: MSB

9-0

THRES2

R/W

10-bits value of threshold 2

Bit0: LSB

Bit9: MSB

8.6.40 THRES_CFG2 Register (Offset = 2Bh) [Reset = 0h]

THRES_CFG2 is shown in Figure 8-63 and described in Table 8-51.

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Figure 8-63 THRES_CFG2 Register

23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED				THRES5										THRES4
R-0h				R-0h										R-0h

LEGEND: R/W = Read/Write; R = Read only

Table 8-51 THRES_CFG2 Register Field Descriptions

Bit

Field

Type

Reset

Description

23-20

RESERVED

Reserved

19-10

THRES5

R/W

10-bits value of threshold 5:

Bit10: LSB

Bit19: MSB

10-1

THRES4

R/W

10-bits value of threshold 4:

Bit0: LSB

Bit9: MSB

8.6.41 THRES_CFG3 Register (Offset = 2Ch) [Reset = X]

THRES_CFG3 is shown in Figure 8-64 and described in Table 8-52.

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Figure 8-64 THRES_CFG3 Register

23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED				THRES6										THRES7
R-0h				R-0h										R-0h

LEGEND: R/W = Read/Write; R = Read only

Table 8-52 THRES_CFG3 Register Field Descriptions

Bit

Field

Type

Reset

Description

23-20

RESERVED

Reserved

19-10

THRES7

R/W

10-bits value of threshold 7:

Bit10: LSB

Bit19: MSB

9-0

THRES6

R/W

10-bits value of threshold 6:

Bit0: LSB

Bit9: MSB

8.6.42 THRES_CFG4 Register (Offset = 2Dh) [Reset = X]

THRES_CFG4 is shown in Figure 8-65 and described in Table 8-53.

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Figure 8-65 THRES_CFG4 Register

23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED				THRES9										THRES8
R-0h				R-0h										R-0h

LEGEND: R/W = Read/Write; R = Read only

Table 8-53 THRES_CFG4 Register Field Descriptions

Bit

Field

Type

Reset

Description

23-20

RESERVED

Reserved

19-10

THRES9

R/W

10-bits value of threshold 9:

Bit10: LSB

Bit19: MSB

9-0

THRES8

R/W

10-bits value of threshold 8:

Bit0: LSB

Bit9: MSB

8.6.43 THRESMAP_CFG0 Register (Offset = 2Eh) [Reset = 0h]

THRESMAP_CFG0 is shown in Figure 8-66 and described in Table 8-54.

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Figure 8-66 THRESMAP_CFG0 Register

23	22	21	20	19	18	17	16	15	14	13	12
THRESMAP_IN7			THRESMAP_IN6			THRESMAP_IN5			THRESMAP_IN4
R/W-0h			R/W-0h			R/W-0h			R/W-0h
11	10	9	8	7	6	5	4	3	2	1	0
THRESMAP_IN3			THRESMAP_IN2			THRESMAP_IN1			THRESMAP_IN0
R/W-0h			R/W-0h			R/W-0h			R/W-0h

LEGEND: R/W = Read/Write

Table 8-54 THRESMAP_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
23-21	THRESMAP_IN7	R/W	0h	0h = THRES0 1h = THRES1 2h = THRES2 3h = THRES3 4h = THRES4 5h = THRES5 6h = THRES6 7h = THRES7
20-18	THRESMAP_IN6	R/W	0h	0h = THRES0 1h = THRES1 2h = THRES2 3h = THRES3 4h = THRES4 5h = THRES5 6h = THRES6 7h = THRES7
17-15	THRESMAP_IN5	R/W	0h	0h = THRES0 1h = THRES1 2h = THRES2 3h = THRES3 4h = THRES4 5h = THRES5 6h = THRES6 7h = THRES7
14-12	THRESMAP_IN4	R/W	0h	0h = THRES0 1h = THRES1 2h = THRES2 3h = THRES3 4h = THRES4 5h = THRES5 6h = THRES6 7h = THRES7
11-9	THRESMAP_IN3	R/W	0h	0h = THRES0 1h = THRES1 2h = THRES2 3h = THRES3 4h = THRES4 5h = THRES5 6h = THRES6 7h = THRES7
8-6	THRESMAP_IN2	R/W	0h	0h = THRES0 1h = THRES1 2h = THRES2 3h = THRES3 4h = THRES4 5h = THRES5 6h = THRES6 7h = THRES7
5-3	THRESMAP_IN1	R/W	0h	0h = THRES0 1h = THRES1 2h = THRES2 3h = THRES3 4h = THRES4 5h = THRES5 6h = THRES6 7h = THRES7
2-0	THRESMAP_IN0	R/W	0h	0h = THRES0 1h = THRES1 2h = THRES2 3h = THRES3 4h = THRES4 5h = THRES5 6h = THRES6 7h = THRES7

8.6.44 THRESMAP_CFG1 Register (Offset = 2Fh) [Reset = 0h]

THRESMAP_CFG1 is shown in Figure 8-67 and described in Table 8-55.

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Figure 8-67 THRESMAP_CFG1 Register

23	22	21	20	19	18	17	16	15	14	13	12
RESERVED						THRESMAP_IN12_IN17_THRES2B			THRESMAP_IN12_IN17_THRES2A
R/W-0h						R/W-0h			R/W-0h
11	10	9	8	7	6	5	4	3	2	1	0
THRESMAP_IN11			THRESMAP_IN10			THRESMAP_IN9			THRESMAP_IN8
R/W-0h			R/W-0h			R/W-0h			R/W-0h

LEGEND: R/W = Read/Write; R = Read only

Table 8-55 THRESMAP_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
23-18	RESERVED	R	0h	Reserved
17-15	THRESMAP_IN12_IN17_THRES2B	R/W	0h	0h = THRES0 1h = THRES1 2h = THRES2 3h = THRES3 4h = THRES4 5h = THRES5 6h = THRES6 7h = THRES7
14-12	THRESMAP_IN12_IN17_THRES2A	R/W	0h	0h = THRES0 1h = THRES1 2h = THRES2 3h = THRES3 4h = THRES4 5h = THRES5 6h = THRES6 7h = THRES7
11-9	THRESMAP_IN11	R/W	0h	0h = THRES0 1h = THRES1 2h = THRES2 3h = THRES3 4h = THRES4 5h = THRES5 6h = THRES6 7h = THRES7
8-6	THRESMAP_IN10	R/W	0h	0h = THRES0 1h = THRES1 2h = THRES2 3h = THRES3 4h = THRES4 5h = THRES5 6h = THRES6 7h = THRES7
5-3	THRESMAP_IN9	R/W	0h	0h = THRES0 1h = THRES1 2h = THRES2 3h = THRES3 4h = THRES4 5h = THRES5 6h = THRES6 7h = THRES7
2-0	THRESMAP_IN8	R/W	0h	0h = THRES0 1h = THRES1 2h = THRES2 3h = THRES3 4h = THRES4 5h = THRES5 6h = THRES6 7h = THRES7

8.6.45 THRESMAP_CFG2 Register (Offset = 30h) [Reset = 0h]

THRESMAP_CFG2 is shown in Figure 8-68 and described in Table 8-56.

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Figure 8-68 THRESMAP_CFG2 Register

23	22	21	20	19	18	17	16	15	14	13	12
RESERVED			THRESMAP_VS1_THRES2B			THRESMAP_VS1_THRES2A			THRESMAP_VS0_THRES2B
R-0h			R/W-0h			R/W-0h			R/W-0h
11	10	9	8	7	6	5	4	3	2	1	0
THRESMAP_VS0_THRES2A			THRESMAP_IN18_IN23_THRES3C			THRESMAP_IN18_IN23_THRES3B			THRESMAP_IN18_IN23_THRES3A
R/W-0h			R/W-0h			R/W-0h			R/W-0h

LEGEND: R/W = Read/Write; R = Read only

Table 8-56 THRESMAP_CFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
23-21	RESERVED	R	0h	Reserved
20-18	THRESMAP_VS1_THRES2B	R/W	0h	0h = THRES0 1h = THRES1 2h = THRES2 3h = THRES3 4h = THRES4 5h = THRES5 6h = THRES6 7h = THRES7
17-15	THRESMAP_VS1_THRES2A	R/W	0h	0h = THRES0 1h = THRES1 2h = THRES2 3h = THRES3 4h = THRES4 5h = THRES5 6h = THRES6 7h = THRES7
14-12	THRESMAP_VS0_THRES2B	R/W	0h	0h = THRES0 1h = THRES1 2h = THRES2 3h = THRES3 4h = THRES4 5h = THRES5 6h = THRES6 7h = THRES7
11-9	THRESMAP_VS0_THRES2A	R/W	0h	0h = THRES0 1h = THRES1 2h = THRES2 3h = THRES3 4h = THRES4 5h = THRES5 6h = THRES6 7h = THRES7
8-6	THRESMAP_IN18_IN23_THRES3C	R/W	0h	0h = THRES0 1h = THRES1 2h = THRES2 3h = THRES3 4h = THRES4 5h = THRES5 6h = THRES6 7h = THRES7
5-3	THRESMAP_IN18_IN23_THRES3B	R/W	0h	0h = THRES0 1h = THRES1 2h = THRES2 3h = THRES3 4h = THRES4 5h = THRES5 6h = THRES6 7h = THRES7
2-0	THRESMAP_IN18_IN23_THRES3A	R/W	0h	0h = THRES0 1h = THRES1 2h = THRES2 3h = THRES3 4h = THRES4 5h = THRES5 6h = THRES6 7h = THRES7

8.6.46 Matrix Register (Offset = 31h) [Reset = 0h]

Matrix is shown in Figure 8-69 and described in Table 8-57.

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Figure 8-69 Matrix Register

23	22	21	20	19	18	17	16	15	14	13	12
RESERVED							IN_COM_EN		THRES_COM
R-0h							R/W-0h		R/W-0h
11	10	9	8	7	6	5	4	3	2	1	0
THRES_COM							MATRIX		POLL_ACT_TIME_M
R/W-0h							R/W-0h		R/W-0h

LEGEND: R/W = Read/Write; R = Read only

Table 8-57 Matrix Register Field Descriptions

Bit	Field	Type	Reset	Description
23-17	RESERVED	R	0h	Reserved
16-15	IN_COM_EN	R/W	0h	0h = no interrupt generation for w.r.t. threshold THRES_COM 1h = interrupt generation on rising edge above threshold THRES_COM 2h = interrupt generation on falling edge below threshold THRES_COM 3h = interrupt generation on falling and rising edge of threshold THRES_COM
14-5	THRES_COM	R/W	0h	10-bits value of threshold THRES_COM: Bit5: LSB Bit14: MSB
4-3	MATRIX	R/W	0h	0h = no matrix, regular inputs only 1h = 4×4 matrix 2h = 5×5 matrix 3h = 6×6 matrix
2-0	POLL_ACT_TIME_M	R/W	0h	Polling active time setting for the matrix inputs: 0h = 64 μs 1h = 128 μs 2h = 256 μs 3h = 384 μs 4h = 512 μs 5h = 768 μs 6h = 1024 μs 7h = 1360 μs

8.6.47 Mode Register (Offset = 32h) [Reset = 0h]

Mode is shown in Figure 8-70 and described in Table 8-58.

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Figure 8-70 Mode Register

23	22	21	20	19	18	17	16	15	14	13	12
M_IN23	M_IN22	M_IN21	M_IN20	M_IN19	M_IN18	M_IN17	M_IN16	M_IN15	M_IN14	M_IN13	M_IN12
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h
11	10	9	8	7	6	5	4	3	2	1	0
M_IN11	M_IN10	M_IN9	M_IN8	M_IN7	M_IN6	M_IN5	M_IN4	M_IN3	M_IN2	M_IN1	M_IN0
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

LEGEND: R/W = Read/Write

Table 8-58 Mode Register Field Descriptions

Bit	Field	Type	Reset	Description
23	M_IN23	R/W	0h	0h = comparator mode for IN23 1h = ADC mode for IN23
22	M_IN22	R/W	0h	0h = comparator mode for IN22 1h = ADC mode for IN22
21	M_IN21	R/W	0h	0h = comparator mode for IN21 1h = ADC mode for IN21
20	M_IN20	R/W	0h	0h = comparator mode for IN20 1h = ADC mode for IN20
19	M_IN19	R/W	0h	0h = comparator mode for IN19 1h = ADC mode for IN19
18	M_IN18	R/W	0h	0h = comparator mode for IN18 1h = ADC mode for IN18
17	M_IN17	R/W	0h	0h = comparator mode for IN17 1h = ADC mode for IN17
16	M_IN16	R/W	0h	0h = comparator mode for IN16 1h = ADC mode for IN16
15	M_IN15	R/W	0h	0h = comparator mode for IN15 1h = ADC mode for IN15
14	M_IN14	R/W	0h	0h = comparator mode for IN14 1h = ADC mode for IN14
13	M_IN13	R/W	0h	0h = comparator mode for IN13 1h = ADC mode for IN13
12	M_IN12	R/W	0h	0h = comparator mode for IN12 1h = ADC mode for IN12
11	M_IN11	R/W	0h	0h = comparator mode for IN11 1h = ADC mode for IN11
10	M_IN10	R/W	0h	0h = comparator mode for IN10 1h = ADC mode for IN10
9	M_IN9	R/W	0h	0h = comparator mode for IN9 1h = ADC mode for IN9
8	M_IN8	R/W	0h	0h = comparator mode for IN8 1h = ADC mode for IN8
7	M_IN7	R/W	0h	0h = comparator mode for IN7 1h = ADC mode for IN7
6	M_IN6	R/W	0h	0h = comparator mode for IN6 1h = ADC mode for IN6
5	M_IN5	R/W	0h	0h = comparator mode for IN5 1h = ADC mode for IN5
4	M_IN4	R/W	0h	0h = comparator mode for IN4 1h = ADC mode for IN4
3	M_IN3	R/W	0h	0h = comparator mode for IN3 1h = ADC mode for IN1
2	M_IN2	R/W	0h	0h = comparator mode for IN2 1h = ADC mode for IN0
1	M_IN1	R/W	0h	0h = comparator mode for IN1 1h = ADC mode for IN1
0	M_IN0	R/W	0h	0h = comparator mode for IN0 1h = ADC mode for IN0