SLLSEV5D July   2017  – June 2019 TIOL111 , TIOL1113 , TIOL1115

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1  Wake Up Detection
      2. 8.3.2  Current Limit Configuration
      3. 8.3.3  Current Fault Detection, Indication and Auto Recovery
      4. 8.3.4  Thermal Warning, Thermal Shutdown
      5. 8.3.5  Fault Reporting (NFAULT)
      6. 8.3.6  Transceiver Function Tables
      7. 8.3.7  The Integrated Voltage Regulator (LDO)
      8. 8.3.8  Reverse Polarity Protection
      9. 8.3.9  Integrated Surge Protection and Transient Waveform Tolerance
      10. 8.3.10 Power Up Sequence (TIOL111)
      11. 8.3.11 Undervoltage Lock-Out (UVLO)
    4. 8.4 Device Functional Modes
      1. 8.4.1 NPN Configuration (N-Switch SIO Mode)
      2. 8.4.2 PNP Configuration (P-Switch SIO Mode)
      3. 8.4.3 Push-Pull, Communication Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Maximum Junction Temperature Check
        2. 9.2.2.2 Driving Capacitive Loads
        3. 9.2.2.3 Driving Inductive Loads
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLIES (L+)
I(L+) Quiescent supply current EN = LOW, no load 1 1.5 mA
EN = HIGH, no load 2 2.7 mA
LOGIC-LEVEL INPUTS (EN, TX)
VIL Input logic low voltage 0.8 V
VIH Input logic high voltage 2 V
RPD Pull-down (EN) resistance 100 kΩ
RPU Pull-up (TX) resistance 200 kΩ
CONTROL OUTPUTS (WAKE, NFAULT)
VOL Output logic low voltage IO = 4 mA 0.5 V
IOZ Output high impedance leakage Output in Hi-Z, VO = 0 V or VCC_IN/OUT –1 1 µA
DRIVER OUTPUT (CQ)
VDS(ON) High-side driver residual voltage I = 250 mA 1.75 V
I = 200 mA 1.5 V
I = 100 mA 1.1 V
Low-side driver residual voltage I = 250 mA 1.75 V
I = 200 mA 1.5 V
I = 100 mA 1.1 V
VIM Voltage between CQ and L- during IO-Link Master wake-up pulse High-side configuration, Rload = 26 Ω between CQ and L-, 18 V ≤ V(L+) ≤ 30 V 14.5 V
Low-side configuration, Rload = 24 Ω between CQ and L+, V(L+) = 20 V 4 V
Low-side configuration, Rload = 44 Ω between CQ and L+, V(L+) = 30 V 4 V
IOZ CQ leakage EN = LOW, 0 ≤ V(CQ) ≤ (V(L+) - 0.1 V) –2 2 µA
IO(LIM) Driver output current limit RSET = 100 kΩ 35 50 70 mA
RSET = 0 kΩ 300 350 400 mA
RSET = OPEN(1) 300 350 400 mA
RECEIVER INPUT (CQ)
V(THH) Input threshold “H” V(L+) > 18 V 10.5 13 V
V(THL) Input threshold “L" 8 11.5 V
V(HYS) Receiver Hysteresis
(V(THH) - V(THL))		 0.75 V
V(THH) Input threshold “H” V(L+) < 18 V See Note (2) See Note (3) V
V(THL) Input threshold “L" See Note (4) See Note (5) V
V(HYS) Receiver Hysteresis
(V(THH) - V(THL))		 0.75 V
VOL RX output low voltage IOL = 4 mA 0.4 V
VOH RX output high voltage IOL = –4 mA VCC_IN/
OUT–0.5		 V
PROTECTION CIRCUITS
V(UVLO) L+ under voltage lockout L+ falling; NFAULT = Hi-Z 6 V
L+ rising; NFAULT = LOW 6.5 V
V(UVLO,HYS) L+ under voltage hysteresis Rising to falling threshold 100 mV
V(UVLO_IN) VCC_IN under voltage lockout (No LDO option) VCC_IN falling; NFAULT = Hi-Z 2.4 V
VCC_IN rising; NFAULT = LOW 2.5 V
V(UVLO,HYS) VCC_IN under voltage hysteresis (No LDO option) Rising to falling threshold 100 mV
T(WRN) Thermal warning Die temperature TJ 125 °C
T(SDN) Thermal shutdown 150 160 °C
T(HYS) Thermal hysteresis for shutdown 10 °C
IREV Leakage current in reverse polarity EN = LOW, TX=x; V(CQ) < V(L-) or
V(CQ) > V(L+), up to |36 V| 		50 µA
EN = LOW, TX=x; V(CQ) < V(L-) or
V(CQ) > V(L+), up to |60 V| 		80 µA
EN = HIGH, TX = LOW; V(CQ to L+) = 3 V 550 µA
EN = HIGH, TX = HIGH; V(CQ to L-) = -3 V 10 µA
LINEAR REGULATOR (LDO)
V(VCC_OUT) Voltage regulator output TIOL1115 4.75 5 5.25 V
TIOL1113 3.13 3.3 3.46 V
V(DROP) Voltage regulator drop-out voltage
(V(L+) – V(VCC_OUT))		 ICC = 20 mA load current TIOL1115 1.9 V
TIOL1113 2.3 V
REG Line regulation (dV(VCC_OUT)/dV(L+)) I(VCC_OUT) = 1 mA 1.7 mV/V
LREG Load regulation (dV(VCC_OUT)/V(VCC_OUT)) V(L+) = 24 V, I(VCC_OUT) = 100 µA to 20 mA 1%
PSSR Power Supply Rejection Ratio 100 kHz, I(VCC_OUT) = 20 mA 40 dB
(1) Current fault indication will be active. Current fault auto recovery will be de-activated.
(2) VTHH (min) = 5 V + (11/18) [V(L+) - 8 V]
(3) VTHH (max) = 6.5 V + (13/18) [V(L+) - 8 V]
(4) VTHL (min) = 4 V + (8/18) [V(L+) -8 V]
(5) VTHL (max) = 6 V + (11/18) [V(L+) -8 V]