Refer to the PDF data sheet for device specific package drawings
Both CQ and DO channels configurable for use in IO-link master modules
The TIOL221 transceiver integrates dual low-power output drivers with active reverse polarity protection. When the device is connected to an IO-Link controller through a three-wire interface, the controller can initiate communication, and exchange data with the remote node while the TIOL221 acts as a complete physical layer for the communication. The device also integrates an auxiliary DI channel.
The device is capable of withstanding up to 1.2kV (500Ω) of IEC 61000-4-5 surge and features integrated reverse polarity protection. In addition to the SPI interface for configurability and expanded diagnostic capability, a simple pin-programmable interface allows easy interfacing with the controller circuits. The output current limit can be configured using either an external resistor or per-configured limits via SPI interface. TIOL221 can be configured to generate wake-up pulse, and be used in IO-link controller applications. Fault reporting and internal protection functions are provided for undervoltage, overcurrent and overtemperature conditions.
PART NUMBER | PACKAGE(1) | PACKAGE SIZE(2) |
---|---|---|
TIOL221 | VQFN (24) | 4mm x 4mm |
DSBGA (25) (3) | 2.7mm x 2.7mm |
PIN NAME | PIN NUMBER | I/O | TYPE | DESCRIPTION | |
---|---|---|---|---|---|
VQFN | DSBGA | ||||
CQ | 8 | A1 | I/O | High Voltage | IO-link signal data pin. |
CS/PP | 1 | E1 | I | Digital | Chip select input pin in the SPI-mode. Push-pull mode selection input in pin-mode |
DI | 12 | A5 | I | High Voltage | DI receiver Input. DI receiver output can be monitored at the RX2 pin. |
DO | 11 | A4 | O | High Voltage | DO driver output. DO is the inverse logic level of the input at the TX2 pin. |
EN1 | 3 | C2 | I | Low voltage Digital | CQ driver enable input signal from the local controller. Logic low sets the CQ output at Hi-Z. Weak internal pull-down. |
EN2 | 19 | E5 | I | Low voltage Digital | DO driver enable input signal from the local controller. Logic low sets the DO output at Hi-Z. Weak internal pull-down. |
ILIM_ADJ1 | 6 | B2 | I | Low voltage Analog | Input for the current limit adjustment for the CQ driver. Connect resistor RSET1 between ILIM_ADJ1 and LM. |
ILIM_ADJ2 | 7 | B3 | I | Low voltage Analog | Input for the current limit adjustment for the DO driver. Connect resistor RSET2 between ILIM_ADJ2 and LM. |
INT/NFLT1 | 20 | E4 | O | Low voltage Digital | Interrupt output, push-pull (SPI-mode) or fault indicator for CQ channel, open-drain (pin-mode) |
LM | 10 | A3 | G | Ground | Ground. |
LP | 9 | A2 | PI | High Voltage | Power supply input (24V typical) to the device. Connect 1µF capacitor to LM (ground) as close to the device as possible. |
NC | -- | C3 | NC | No Connect | Not connected internally. |
RX1 | 2 | D1 | O | Low voltage Digital | C/Q Receiver Logic Output. RX2 is the inverse logic level of the signal on the CQ input. |
RX2 | 15 | C5 | O | Low voltage Digital | DI Receiver Logic Output. RX2 is the inverse logic level of the signal on the DI input. |
SCK | 22 | E3 | I | Low voltage Digital | SPI clock input |
SDI/NPN | 24 | E2 | I | Low voltage Digital | SPI serial data input (SPI-mode) Or NPN mode selector (pin-mode) |
SDO/NFLT2 | 21 | D3 | O | Low voltage Digital | SPI serial data output, push-pull (SPI-mode) or fault inductor for DO channel, open-drain (pin-mode) |
SPI/PIN | 23 | D2 | I | Low voltage Digital | SPI or pin-mode selection input. Drive this pin low for pin-mode operation. Drive this pin high for SPI-mode control. |
TX1 | 4 | C1 | I | Low voltage Digital | CQ driver input data from local microcontroller. Weak internal pull-up. |
TX2 | 17 | D5 | I | Low voltage Digital | DO driver input data from local microcontroller. Weak internal pull-up. |
VOUT | 13 | B4 | PO | Low voltage | LDO regulator output. Output level determined by VSEL pin |
VSEL | 16 | C4 | I | Low voltage |
|
RESET | 14 | B1 | O | Low voltage | Reset output pin, open-drain, active low. The pin behaves as a reset pin to indicate UV on LP or VOUT. |
V5IN | 5 | B5 | PI | Low voltage | (Optional) Connect this pin 5V supply input from external regulator to reduce the power dissipation from the internal regulator. Leave the pin floating if unused. |
WU | 18 | D4 | O | Low voltage Digital | Wake-up indicator to the local microcontroller. Open-drain output, connect this pin via pull-up resistor to VOUT. |
Thermal Pad | Thermal Pad | N/A | G | Ground | Connect the exposed thermal pad to ground (LM) for optimal thermal and electrical performance |
MIN | MAX | UNIT | ||
---|---|---|---|---|
LP, CQ, DO, DI | Steady state voltage for LP, CQ, DO and DI | –65 | 65 | V |
Transient pulse width < 100 µs for LP, CQ, DO and DI | –70 | 70 | V | |
|V(LP) – V(CQ)|, |V(LP) – V(DO)|, |V(LP) – V(DI)|, |V(CQ) – V(DO)|, |V(CQ) – V(DI)|, |V(DO) – V(DI)| | Voltage drop between bus pins | 65 | V | |
VOUT | Regulator output voltage | –0.3 | 6 | V |
TX1, TX2, EN1, EN2, VSEL, RX1, RX2, CS/PP, SDI/NPN, SDO/NFLT2, SCK, INT/NFLT1, WU, ILIM_ADJ1, ILIM_ADJ2, SPI/PIN | Logic pin voltage | –0.3 | min(VOUT+0.3, 6) | V |
Output current | RX1, RX2, WU, INT/NFLT1, SDO/NFLT2, | –5 | 5 | mA |
Storage temperature, Tstg | -55 | 170 | °C |
VALUE | UNIT | ||||
---|---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | All pins | ±4000 | V |
V(ESD) | Electrostatic discharge | Charged Device Model (CDM), per ANSI/ESDA/JEDEC JS-002 (2) | All pins | ±750 | V |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | IEC 61000-4-2 ESD (Contact Discharge), LP, CQ, DO, DI and LM (1) (2) | ±8,000 | V |
Electrostatic discharge | IEC 61000-4-5, 1.2 µs/50 µs Surge with 500 Ω in series, LP, CQ, DO, DI and LM (1) | ±1,200 | ||
Electrostatic discharge | IEC 61000-4-4 EFT (Fast transient or burst), LP, CQ, DO, DI and LM (1) | ±4,000 |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
V(LP) | 24V Input Supply Voltage | 7 | 24 | 36 | V | |
V(V5IN) | 5V Input Supply Voltage | 5V Input Supply Voltage | 4.5 | 5 | 5.5 | V |
V(I) | Logic level input voltage at TX1, TX2, EN1, EN2,CS/PP, SDI/NPN, SCK, SPI/PIN | 3.3 V configuration | 3 | 3.3 | 3.6 | |
5 V configuration | 4.5 | 5 | 5.5 | V | ||
1/tBIT | Data rate (Communication mode) | 250 | kbps | |||
I(VOUT) | LDO output current | 20 | mA | |||
TA | Operating ambient temperature | –40 | 125 | °C | ||
TJ | Junction temperature | -40 | 150 | °C |