SLLSFS6A September 2024 – December 2024 TIOL221

PRODMIX

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)

RGE|24

Thermal pad, mechanical data (Package|Pins)

Orderable Information

9 TIOL221 Registers

Table 9-1 lists the memory-mapped registers for the TIOL221 registers. All register offset addresses not listed in Table 9-1 should be considered as reserved locations and the register contents should not be modified.

Table 9-1 TIOL221 Registers

Address	Acronym	Register Name	Section
0h	INT	Interrupt	Go
1h	STATUS	Status	Go
2h	DEVICE_CONFIG	Device Configuration	Go
3h	CQ_CURLIM	CQ Driver Current Limit	Go
4h	CQ_CONFIG	CQ Configuration	Go
5h	DIO_CONFIG	DIO Configuration	Go
6h	DO_CURLIM	DO Driver current limit	Go
7h	DEVICE_ID	Device ID	Go
8h	INT_MASK	Interrupt Mask	Go
9h	RESET_CONFIG	Reset pin configuration register	Go

Complex bit access types are encoded to fit into small table cells. Table 9-2 shows the codes that are used for access types in this section.

Table 9-2 TIOL221 Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
RC	R C	Read to Clear
Write Type
W	W	Write
Reset or Default Value
-n		Value after reset or the default value

9.1 INT Register (Address = 0h) [Reset = 00h]

INT is shown in Figure 9-1 and described in Table 9-3.

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Interrupt registers reflect current status of various fault conditions. Interrupt registers are not cleared automatically after the fault clears. They are cleared on read if the fault condition does not exist

Figure 9-1 INT Register

7	6	5	4	3	2	1	0
TSD_INT	WU_INT	DO_FAULT_INT	CQ_FAULT_INT	LPW_INT	RESERVED	UV_V5_INT	TEMP_WARN
RC-0b	RC-0b	RC-0b	RC-0b	RC-0b	R-0b	RC-0b	RC-0b

Table 9-3 INT Register Field Descriptions

Bit	Field	Type	Reset	Description
7	TSD_INT	RC	0b	Thermal shutdown interrupt bit. This bit is not cleared automatically when the fault is cleared. The bit is cleared on read if the fault does not exist anymore 0b = The device is not in thermal shutdown 1b = The device has entered thermal shutdown
6	WU_INT	RC	0b	This bit is set when an IO-link wake-up condition is detected on CQ. 0b = No wake-up detected 1b = Wake-up detected
5	DO_FAULT_INT	RC	0b	This bit is set when DO driver fault occurs (overcurrent or thermal) 0b = No fault on DO driver 1b = DO driver fault has occurred
4	CQ_FAULT_INT	RC	0b	This bit is set when CQ driver fault occurs (overcurrent or thermal) 0b = No fault on CQ driver 1b = CQ driver fault has occurred
3	LPW_INT	RC	0b	This bit is set when LP goes below the warning threshold 0b = LP is above the warning threshold 1b = LP has fallen below the warning threshold
2	RESERVED	R	0b	Reserved
1	UV_V5_INT	RC	0b	Undervoltage on the V5IN supply input (valid only if VSEL pin is floating and V5IN is the LDO input) 0b = No UV fault on V5IN 1b = UV fault on V5IN
0	TEMP_WARN	RC	0b	Thermal warning interrupt 0b = No thermal warning 1b = Thermal warning limit reached

9.2 STATUS Register (Address = 1h) [Reset = 00h]

STATUS is shown in Figure 9-2 and described in Table 9-4.

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Status registers reflect current status of various fault conditions. They are read-only and cleared automatically when the fault is cleared. Note: Soft reset does not reset the STATUS register bits as they reflect the current status of the faults. It is recommended to read the MSB byte when reading the STATUS register because the POR recovery bit is cleared by the time LSB byte is transferred to data output

Figure 9-2 STATUS Register

7	6	5	4	3	2	1	0
POR_RECOVERY	TSD	DI_LEVEL	DO_FAULT	CQ_FAULT	UV_V5	CQ_RX_LEVEL	TEMP_WARN
RC-0b	R-0b	R-0b	R-0b	R-0b	R-0b	R-0b	R-0b

Table 9-4 STATUS Register Field Descriptions

Bit	Field	Type	Reset	Description
7	POR_RECOVERY	RC	0b	The bit is set when the device recovers from POR event. The bit is cleared on read 0b = The device is operating normally 1b = The device has recovered from POR event
6	TSD	R	0b	The bit reflects the status of thermal shutdown. The bit is automatically cleared when temperature falls below thermal shutdown threshold 0b = No thermal shutdown 1b = Part in thermal shutdown
5	DI_LEVEL	R	0b	This bit is set when DI voltage is logic high and cleared when DI voltage is logic low Note: This bit is invalid if DI_DIS bit is set to 1. 0b = 0x0 1b = 0x1
4	DO_FAULT	R	0b	The bit reflects the status of DO drive fault 0b = No fault at DO pin 1b = Fault at DO pin
3	CQ_FAULT	R	0b	This bit reflects the status of the CQ driver fault 0b = No fault at CQ pin 1b = Fault at CQ pin
2	UV_V5	R	0b	This bit reflects the status of the UV condition at the V5IN pin 0b = V5IN voltage above UVLO threshold 1b = V5IN below UVLO threshold
1	CQ_RX_LEVEL	R	0b	This bit is set when CQ voltage is logic high and cleared when CQ voltage is logic low. Note: This bit is invalid if CQ_RX_DIS bit is set to 1. 0b = 0x0 1b = 0x1
0	TEMP_WARN	R	0b	Shows the status of the device temperature above or below the temperature warning threshold 0b = No temperature warning 1b = Device temperature is above the warning threshold

9.3 DEVICE_CONFIG Register (Address = 2h) [Reset = 00h]

DEVICE_CONFIG is shown in Figure 9-3 and described in Table 9-5.

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Device level configuration registers

Figure 9-3 DEVICE_CONFIG Register

7	6	5	4	3	2	1	0
SOFT_RESET	WU_DIS	DO_CQ_TRACK	IOLINK_5MA_PD	DI_RX_FILTER	CQ_RX_FILTER	T_UVLO	INT_TOG
R/W-0b	R/W-0b	R/W-0b	R/W-0b	R/W-0b	R/W-0b	R/W-0b	R/W-0b

Table 9-5 DEVICE_CONFIG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	SOFT_RESET	R/W	0b	Resets all registers to their defaults. Note: The status and interrupt bits may still be set depending upon the corresponding fault status. 0b = No reset 1b = Resets the device configuration
6	WU_DIS	R/W	0b	0b = CQ can recognize wake-up pulse 1b = CQ ignores the wake-up pulse
5	DO_CQ_TRACK	R/W	0b	If the bit is set, DO and CQ drivers both track together as a function of the TX input and CQ_CONFIG setting. 0b = DO and CQ drivers are independent 1b = DO and CQ drivers track as a function of the TX input
4	IOLINK_5MA_PD	R/W	0b	Enables 5mA pull-down current ILLM at both CQ and DO drivers when the respective driver is disabled. Note: CQ_CUR_LIM and DO_CUR_LIM limit needs to be set to 500mA to enable this respectively at CQ and DO. 0b = 5mA (min) pull-down current disabled 1b = 5mA (min) pull-down current enabled when the respective driver is disabled
3	DI_RX_FILTER	R/W	0b	Turns on or off the RX glitch filter on the DI line 0b = DI glitch filter disabled 1b = DI glitch filter enabled
2	CQ_RX_FILTER	R/W	0b	Turns on or off the RX glitch filter on the CQ line 0b = CQ RX glitch filter disabled 1b = CQ RX glitch filter enabled
1	T_UVLO	R/W	0b	CQ, DO re-enable delay, t(UVLO), after the recovery from LP UVLO 0b = 0.5 ms (typ) 1b = 30 ms (typ)
0	INT_TOG	R/W	0b	Enables interrupt pin toggling 0b = Interrupt pin set to active low 1b = Interrupt pin set to toggle with 200us period and 50% duty cycle

9.4 CQ_CURLIM Register (Address = 3h) [Reset = 20h]

CQ_CURLIM is shown in Figure 9-4 and described in Table 9-6.

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CQ Driver current limit and auto-retry configuration

Figure 9-4 CQ_CURLIM Register

7	6	5	4	3	2	1	0
CQ_CUR_LIM			CQ_BL_TIME		CQ_RETRY_TIME		CQ_AUTO_RETRY_EN
R/W-001b			R/W-00b		R/W-00b		R/W-0b

Table 9-6 CQ_CURLIM Register Field Descriptions

Bit	Field	Type	Reset	Description
7-5	CQ_CUR_LIM	R/W	001b	Sets current limits 000b = 35 mA (min) 001b = 50 mA (min) 010b = 100 mA (min) 011b = 150 mA (min) 100b = 200 mA (min) 101b = 250 mA (min) 110b = 300 mA (min) 111b = 500 mA (min)
4-3	CQ_BL_TIME	R/W	00b	Sets current blanking time 00b = 200 µs (typ) 01b = 500 µs (typ) 10b = 5 ms (typ) 11b = 0 s (no blanking time)
2-1	CQ_RETRY_TIME	R/W	00b	Sets auto re-try time 00b = 50 ms (typ) 01b = 100 ms (typ) 10b = 200 ms (typ) 11b = 500 ms (typ)
0	CQ_AUTO_RETRY_EN	R/W	0b	Enable auto re-try. When enabled the driver gets disabled after blanking time and re-enabled after the retry time. When auto retry is disabled, the driver stays enabled and shut off only after thermal shutdown NOTE: It is not recommended to enable auto retry when blanking time is configured to 2b11 (no blanking time) . 0b = Disabled 1b = Enabled

9.5 CQ_CONFIG Register (Address = 4h) [Reset = 0Ch]

CQ_CONFIG is shown in Figure 9-5 and described in Table 9-7.

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CQ configration registers for PNP/NPN modes and weak pull-up/down

Figure 9-5 CQ_CONFIG Register

7	6	5	4	3	2	1	0
RESERVED		CQ_WEAK_PD_EN	CQ_WEAK_PU_EN	CQ_TX_MODE		CQ_Q	RX_DIS
R-0b		R/W-0b	R/W-0b	R/W-11b		R/W-0b	R/W-0b

Table 9-7 CQ_CONFIG Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R	0b	Reserved
5	CQ_WEAK_PD_EN	R/W	0b	Configures the weak pull-down on CQ when the driver is disabled 0b = Weak pull-down disabled 1b = Weak pull-down enabled
4	CQ_WEAK_PU_EN	R/W	0b	Configures the weak pull-up on CQ when the driver is disabled 0b = Weak pull-up disabled 1b = Weak pull-up enabled
3-2	CQ_TX_MODE	R/W	11b	Configures the driver transmission mode 00b = PNP mode 01b = Push-pull mode 10b = NPN mode 11b = Driver disabled
1	CQ_Q	R/W	0b	CQ driver output logic 0b = CQ is in high-impedance when EN1 is low (or CQ_DIS is low) 1b = CQ driver outputs logic high in push-pull or PNP mode and is turned-off in NPN mode
0	RX_DIS	R/W	0b	Configures the RX of the CQ line 0b = RX is enabled 1b = RX is disabled

9.6 DIO_CONFIG Register (Address = 5h) [Reset = 0Ch]

DIO_CONFIG is shown in Figure 9-6 and described in Table 9-8.

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Figure 9-6 DIO_CONFIG Register

7	6	5	4	3	2	1	0
DI_WEAK_PD_EN	DI_WEAK_PU_EN	DO_WEAK_PD_EN	DO_WEAK_PU_EN	DO_MODE		DO_Q	DI_DIS
R/W-0b	R/W-0b	R/W-0b	R/W-0b	R/W-11b		R/W-0b	R/W-0b

Table 9-8 DIO_CONFIG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	DI_WEAK_PD_EN	R/W	0b	Configures the weak pull-down on DI 0b = Weak pull-down disabled 1b = Weak pull-down enabled
6	DI_WEAK_PU_EN	R/W	0b	Configures the weak pull-up on DI 0b = Weak pull-up disabled 1b = Weak pull-up enabled
5	DO_WEAK_PD_EN	R/W	0b	Configures the weak pull-down on DO when the driver is disabled 0b = Weak pull-down disabled 1b = Weak pull-down enabled
4	DO_WEAK_PU_EN	R/W	0b	Configures the weak pull-up on DO when the driver is disabled 0b = Weak pull-up disabled 1b = Weak pull-up enabled
3-2	DO_MODE	R/W	11b	Configures the DO driver transmission mode 00b = PNP mode 01b = Push-pull mode 10b = NPN mode 11b = Driver disabled
1	DO_Q	R/W	0b	DO driver output logic 0b = DO is in high-impedance when EN2 is low (or DO_DIS is low) 1b = DO driver outputs logic high in push-pull or PNP mode and is turned-off in NPN mode
0	DI_DIS	R/W	0b	Configures the DI receiver 0b = DI is enabled 1b = DI is disabled

9.7 DO_CURLIM Register (Address = 6h) [Reset = 20h]

DO_CURLIM is shown in Figure 9-7 and described in Table 9-9.

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DO Driver current limit and auto-retry configuration

Figure 9-7 DO_CURLIM Register

7	6	5	4	3	2	1	0
DO_CUR_LIM			DO_BL_TIME		DO_RETRY_TIME		DO_RETRY_EN
R/W-001b			R/W-00b		R/W-00b		R/W-0b

Table 9-9 DO_CURLIM Register Field Descriptions

Bit	Field	Type	Reset	Description
7-5	DO_CUR_LIM	R/W	001b	Sets current limits 000b = 35 mA (min) 001b = 50 mA (min) 010b = 100 mA (min) 011b = 150 mA (min) 100b = 200 mA (min) 101b = 250 mA (min) 110b = 300 mA (min) 111b = 500 mA (min)
4-3	DO_BL_TIME	R/W	00b	Sets current blanking time. NOTE: It is not recommended to configure 0b11 (no blanking time) when Auto retry is enabled. 00b = 200 µs (typ) 01b = 500 µs (typ) 10b = 5 ms (typ) 11b = 0 s (no blanking time)
2-1	DO_RETRY_TIME	R/W	00b	Sets auto re-try time NOTE: It is not recommended to enable auto retry when blanking time is configured to 2b11 (no blanking time) . 00b = 50 ms (typ) 01b = 100 ms (typ) 10b = 200 ms (typ) 11b = 500 ms (typ)
0	DO_RETRY_EN	R/W	0b	Enable auto re-try 0b = Disabled 1b = Enabled

9.8 DEVICE_ID Register (Address = 7h) [Reset = 01h]

DEVICE_ID is shown in Figure 9-8 and described in Table 9-10.

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Figure 9-8 DEVICE_ID Register

7	6	5	4	3	2	1	0
RESERVED					Revision ID
R-0b					R-001b

Table 9-10 DEVICE_ID Register Field Descriptions

Bit	Field	Type	Reset	Description
7-3	RESERVED	R	0b	Reserved
2-0	Revision ID	R	001b	Indicates the device revision number 001b = 1st revision

9.9 INT_MASK Register (Address = 8h) [Reset = 00h]

INT_MASK is shown in Figure 9-9 and described in Table 9-11.

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Interrupt masking registers. When an interrupt is masked, the interrupt pin does not indicate the interrupt but the interrupt register is still updated to indicate the interrupt.

Figure 9-9 INT_MASK Register

7	6	5	4	3	2	1	0
TSD_INT_MASK	WU_INT_MASK	DO_FAULT_INT_MASK	CQ_FAULT_INT_MASK	LPW_INT_MASK	RESERVED	UV_V5_INT_MASK	TEMP_WARN_MASK
R/W-0b	R/W-0b	R/W-0b	R/W-0b	R/W-0b	R-0b	R/W-0b	R/W-0b

Table 9-11 INT_MASK Register Field Descriptions

Bit	Field	Type	Reset	Description
7	TSD_INT_MASK	R/W	0b	0b = Interrupt active 1b = Interrupt masked
6	WU_INT_MASK	R/W	0b	0b = Interrupt active 1b = Interrupt masked
5	DO_FAULT_INT_MASK	R/W	0b	0b = Interrupt active 1b = Interrupt masked
4	CQ_FAULT_INT_MASK	R/W	0b	0b = Interrupt active 1b = Interrupt masked
3	LPW_INT_MASK	R/W	0b	0b = Interrupt active 1b = Interrupt masked
2	RESERVED	R	0b	Reserved
1	UV_V5_INT_MASK	R/W	0b	0b = Interrupt active 1b = Interrupt masked
0	TEMP_WARN_MASK	R/W	0b	0b = Interrupt active 1b = Interrupt masked

9.10 RESET_CONFIG Register (Address = 9h) [Reset = 00h]

RESET_CONFIG is shown in Figure 9-10 and described in Table 9-12.

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Configures the behavior of the RESET pin

Figure 9-10 RESET_CONFIG Register

7	6	5	4	3	2	1	0
RESET_SEL		RESET_POL	RESERVED
R/W-00b		R-0b	R-0b

Table 9-12 RESET_CONFIG Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESET_SEL	R/W	00b	Selects which events will activate the reset output 00b = Both UVLP and UVOUT 01b = UVLP 10b = UVOUT 11b = Reserved
5	RESET_POL	R	0b	Selects between active low and active high configuration for reset output 0b = Pin output low (active-low) 1b = Pin output high (active-high)
4-0	RESERVED	R	0b	Reserved