SLOS081N February   1977  – June 2024 TL081 , TL081A , TL081B , TL081H , TL082 , TL082A , TL082B , TL082H , TL084 , TL084A , TL084B , TL084H

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information for Single Channel
    5. 5.5  Thermal Information for Dual Channel
    6. 5.6  Thermal Information for Quad Channel
    7. 5.7  Electrical Characteristics: TL08xH
    8. 5.8  Electrical Characteristics (DC): TL08xC, TL08xAC, TL08xBC, TL08xI, TL08xM
    9. 5.9  Electrical Characteristics (AC): TL08xC, TL08xAC, TL08xBC, TL08xI, TL08xM
    10. 5.10 Typical Characteristics: TL08xH
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Total Harmonic Distortion
      2. 7.3.2 Slew Rate
    4. 7.4 Device Functional Modes
  9. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Inverting Amplifier Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
    3. 8.3 System Examples
      1. 8.3.1 General Applications
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Examples
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
  • DBV|5
  • DCK|5
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.7 Electrical Characteristics: TL08xH

For VS = (VCC+) – (VCC–) = 4.5V to 40V (±2.25V to ±20V) at TA = 25°C, RL = 10kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage ±1 ±4 mV
TA = –40°C to 125°C ±5
dVOS/dT Input offset voltage drift TA = –40°C to 125°C ±2 µV/℃
PSRR Input offset voltage versus power supply VS = 5V to 40V, VCM = VS / 2 TA = –40°C to 125°C ±1 ±10 μV/V
Channel separation f = 0Hz 10 µV/V
INPUT BIAS CURRENT
IB Input bias current  ±1 ±120 pA
DCK and DBV packages ±1 ±300 pA
TA = –40°C to 125°C (1) ±5 nA
IOS Input offset current  ±0.5 ±120 pA
DCK and DBV packages ±0.5 ±250 pA
TA = –40°C to 125°C (1) ±5 nA
NOISE
EN Input voltage noise f = 0.1Hz to 10Hz   9.2 μVPP
  1.4   µVRMS
eN Input voltage noise density f = 1kHz 37   nV/√Hz
f = 10kHz   21  
iN Input current noise f = 1kHz   80 fA/√Hz
INPUT VOLTAGE RANGE
VCM Common-mode voltage range (VCC–) + 1.5 (VCC+) V
CMRR Common-mode rejection ratio VS = 40V, (VCC–) + 2.5V < VCM < (VCC+) – 1.5V 100 105 dB
TA = –40°C to 125°C 95 dB
VS = 40V, (VCC–) + 2.5V < VCM < (VCC+) 90 105 dB
TA = –40°C to 125°C 80 dB
INPUT CAPACITANCE
ZID Differential 100 || 2 MΩ ||pF
ZICM Common-mode 6 || 1 TΩ ||pF
OPEN-LOOP GAIN
AOL Open-loop voltage gain VS = 40V, VCM = VS / 2,
(VCC–) + 0.3V < VO < (VCC+) –  0.3V		 TA = –40°C to 125°C 118 125 dB
AOL Open-loop voltage gain VS = 40V, VCM = VS / 2, RL = 2kΩ, (VCC–) + 1.2V < VO < (VCC+) –  1.2V TA = –40°C to 125°C 115 120 dB
FREQUENCY RESPONSE
GBW Gain-bandwidth product 5.25 MHz
SR Slew rate VS = 40V, G = +1, CL = 20pF 20 V/μs
tS Settling time To 0.1%, VS = 40V, VSTEP = 10V , G = +1, CL = 20pF 0.63 μs
To 0.1%, VS = 40V, VSTEP = 2V , G = +1, CL = 20pF 0.56
To 0.01%, VS = 40V, VSTEP = 10V , G = +1, CL = 20pF 0.91
To 0.01%, VS = 40V, VSTEP = 2V , G = +1, CL = 20pF 0.48
Phase margin G = +1, RL = 10kΩ, CL = 20pF 56 °
Overload recovery time VIN  × gain > VS 300 ns
THD+N Total harmonic distortion + noise VS = 40V, VO = 6VRMS, G = +1, f = 1kHz 0.00012 %
EMIRR EMI rejection ratio f = 1GHz 53 dB
OUTPUT
  Voltage output swing from rail Positive rail headroom VS = 40V, RL = 10kΩ   115 210 mV
VS = 40V, RL = 2kΩ   520 965
Negative rail headroom VS = 40V, RL = 10kΩ   105 215
VS = 40V, RL = 2kΩ   500 1030
ISC Short-circuit current ±26 mA
CLOAD Capacitive load drive 300
 pF
ZO Open-loop output impedance f = 1MHz, IO = 0 A 125 Ω
POWER SUPPLY
IQ Quiescent current per amplifier IO = 0 A 937.5 1125 µA
IO = 0 A, (TL081H) 960 1156
IO = 0 A TA = –40°C to 125°C 1130
IO = 0 A, (TL082H) 1143
IO = 0 A, (TL071H) 1160
Turn-On Time At TA = 25°C, VS = 40V, VS ramp rate > 0.3V/µs
 60 μs
(1) Max IB and Ios data is specified based on characterization results.