SLLS177I March 1994 – March 2021 TL16C550C
PRODUCTION DATA
The ACE contains a programmable baud generator that takes a clock input in the range between dc and 16 MHz and divides it by a divisor in the range between 1 and (216−1).The output frequency of the baud generator is sixteen times (16 x) the baud rate. The formula for the divisor is:
Two 8-bit registers, called divisor latches, store the divisor in a 16-bit binary format. These divisor latches must be loaded during initialization of the ACE in order to ensure desired operation of the baud generator. When either of the divisor latches is loaded, a 16-bit baud counter is also loaded to prevent long counts on initial load.
Table 7-9 and Table 7-10 illustrate the use of the baud generator with crystal frequencies of 1.8432 MHz and 3.072 MHz respectively. For baud rates of 38.4 kbits/s and below, the error obtained is very small. The accuracy of the selected baud rate is dependent on the selected crystal frequency (refer to Figure 7-5 for examples of typical clock circuits).
DESIRED BAUD RATE | DIVISOR USED TO GENERATE 16 x CLOCK | PERCENT ERROR DIFFERENCE BETWEEN DESIRED AND ACTUAL |
---|---|---|
50 | 2304 | |
75 | 1536 | |
110 | 1047 | 0.026 |
134.5 | 857 | 0.058 |
150 | 768 | |
300 | 384 | |
600 | 192 | |
1200 | 96 | |
1800 | 64 | |
2000 | 58 | 0.69 |
2400 | 48 | |
3600 | 32 | |
4800 | 24 | |
7200 | 16 | |
9600 | 12 | |
19200 | 6 | |
38400 | 3 | |
56000 | 2 | 2.86 |
DESIRED BAUD RATE | DIVISOR USED TO GENERATE 16 x CLOCK | PERCENT ERROR DIFFERENCE BETWEEN DESIRED AND ACTUAL |
---|---|---|
50 | 3840 | |
75 | 2560 | |
110 | 1745 | 0.026 |
134.5 | 1428 | 0.034 |
150 | 1280 | |
300 | 640 | |
600 | 320 | |
1200 | 160 | |
1800 | 107 | 0.312 |
2000 | 96 | |
2400 | 80 | |
3600 | 53 | 0.628 |
4800 | 40 | |
7200 | 27 | 1.23 |
9600 | 20 | |
19200 | 10 | |
38400 | 5 |
CRYSTAL | RP | RX2 | C1 | C2 |
---|---|---|---|---|
3.072 MHz | 1 MW | 1.5 kW | 10 − 30 pF | 40 − 60 pF |
1.8432 MHz | 1 MW | 1.5 kW | 10 − 30 pF | 40 − 60 pF |