(1)The LSR provides information to the CPU concerning
the status of data transfers. The contents of this register are summarized in Table 7-3 and described in the following bulleted list.
- Bit 0: This bit is the data ready
(DR) indicator for the receiver. DR is set whenever a complete incoming character
has been received and transferred into the RBR or the FIFO. DR is cleared by reading
all of the data in the RBR or the FIFO.
- Bit 1(1):This bit is
the overrun error (OE) indicator. When OE is set, it indicates that before the
character in the RBR was read, it was overwritten by the next character transferred
into the register. OE is cleared every time the CPU reads the contents of the LSR.
If the FIFO mode data continues to fill the FIFO beyond the trigger level, an
overrun error occurs only after the FIFO is full and the next character has been
completely received in the shift register. An overrun error is indicated to the CPU
as soon as it happens. The character in the shift register is overwritten, but it is
not transferred to the FIFO.
- Bit 2 (see Footnote 2): This
bit is the parity error (PE) indicator. When PE is set, it indicates that the parity
of the received data character does not match the parity selected in the LCR (bit
4). PE is cleared every time the CPU reads the contents of the LSR. In the FIFO
mode, this error is associated with the particular character in the FIFO to which it
applies. This error is revealed to the CPU when its associated character is at the
top of the FIFO.
- Bit 3 (see Footnote 2): This
bit is the framing error (FE) indicator. When FE is set, it indicates that the
received character didnot have a valid (set) stop bit. FE is cleared every time the
CPU reads the contents of the LSR. In the FIFO mode, this error is associated with
the particular character in the FIFO to which it applies. This error is revealed to
the CPU when its associated character is at the top of the FIFO. The ACE tries to
resynchronize after a framing error. To accomplish this, it is assumed that the
framing error is due to the next start bit. The ACE samples this start bit twice and
then accepts the input data.
- Bit 4 (see Footnote 2): This
bit is the break interrupt (BI) indicator. When BI is set, it indicates that the
received data input was held low for longer than a full-word transmission time. A
full-word transmission time is defined as the total time to transmit the start,
data, parity, and stop bits. BI is cleared every time the CPU reads the contents of
the LSR. In the FIFO mode, this error is associated with the particular character in
the FIFO to which it applies. This error is revealed to the CPU when its associated
character is at the top of the FIFO. When a break occurs, only one 0 character is
loaded into the FIFO. The next character transfer is enabled after SIN goes to the
marking state for at least two RCLK samples and then receives the next valid start
bit.
- Bit 5: This bit is the THRE
indicator. THRE is set when the THR is empty, indicating that the ACE is ready to
accept a new character. If the THRE interrupt is enabled when THRE is set, an
interrupt is generated. THRE is set when the contents of the THR are transferred to
the TSR. THRE is cleared concurrent with the loading of the THR by the CPU. In the
FIFO mode, THRE is set when the transmit FIFO is empty; it is cleared when at least
one byte is written to the transmit FIFO.
- Bit 6: This bit is the transmitter
empty (TEMT) indicator. TEMT bit is set when the THR and the TSR are bothempty. When
either the THR or the TSR contains a data character, TEMT is cleared. In the FIFO
mode, TEMT is set when the transmitter FIFO and shift register are both empty.
- Bit 7: In the TL16C550C mode, this
bit is always cleared. In the TL16C450 mode, this bit is always cleared. In the FIFO
mode, LSR7 is set when there is at least one parity, framing, or break error in the
FIFO. It is cleared when the microprocessor reads the LSR and there are no
subsequent errors in the FIFO.