8.3.1 Functional Description

The TL16C752C UART can be placed in an alternate mode (FIFO mode) relieving the processor of excessive software overhead by buffering received and transmitted characters. Both the receiver and transmitter FIFOs can store up to 64 bytes (including three additional bits of error status per byte for the receiver FIFO) and have selectable or programmable trigger levels. Primary outputs RXRDY and TXRDY allow signaling of DMA transfers.

The TL16C752C UART has selectable hardware flow control and software flow control. Both schemes significantly reduce software overhead and increase system efficiency by automatically controlling serial data flow. Hardware flow control uses the RTS output and CTS input signals. Software flow control uses programmable Xon and Xoff characters.

The TL16C752C device includes a programmable baud rate generator that can divide the timing reference clock by a divisor between 1 and 65535. A bit (MCR7) can be used to invoke a prescaler (divide by 4) off the reference clock, prior to the baud rate generator input. The divide by 4 prescaler is selected when MCR7 is set to 1.

8.3.1.3 Auto-RTS

Auto-RTS data flow control originates in the receiver block (see Figure 14). Figure 16 shows RTS functional timing. The receiver FIFO trigger levels used in Auto-RTS are stored in the TCR. RTS is active if the RX FIFO level is below the HALT trigger level in TCR[3:0]. When the receiver FIFO HALT trigger level is reached, RTS is deasserted. The sending device (for example, another UART) may send an additional byte after the trigger level is reached (assuming the sending UART has another byte to send) because it may not recognize the deassertion of RTS until it has begun sending the additional byte. RTS is automatically reasserted once the receiver FIFO reaches the RESUME trigger level programmed via TCR[7:4]. This reassertion allows the sending device to resume transmission.

A. N = receiver FIFO trigger level B.

B. The two blocks in dashed lines cover the case where an additional byte is sent as described in Auto-RTS.

Figure 16. RTS Functional Timing

8.3.1.4 Auto-CTS

The transmitter circuitry checks CTS before sending the next data byte. When CTS is active, the transmitter sends the next byte. To stop the transmitter from sending the following byte, CTS must be deasserted before the middle of the last stop bit that is currently being sent. The auto-CTS function reduces interrupts to the host system. When flow control is enabled, the CTS state changes and need not trigger host interrupts because the device automatically controls its own transmitter. Without auto-CTS, the transmitter sends any data present in the transmit FIFO and a receiver overrun error can result. Figure 17 shows CTS functional timing, and Figure 18 shows an example of autoflow control.

A. When CTS is low, the transmitter keeps sending serial data out.

B. When CTS goes high before the middle of the last stop bit of the current byte, the transmitter finishes sending the current byte, but it does not send the next byte.

C. When CTS goes from high to low, the transmitter begins sending data again.

Figure 17. CTS Functional Timing

Figure 18. Autoflow Control (Auto-RTS and Auto-CTS) Example

8.3.1.5 Software Flow Control

Software flow control is enabled through the enhanced feature register and the modem control register. Different combinations of software flow control can be enabled by setting different combinations of EFR[3−0]. Table 1 shows software flow control options.

Two other enhanced features relate to software flow control:

• Xon Any Function [MCR(5): Operation resumes after receiving any character after recognizing the Xoff character.
• Special Character [EFR(5)]: Incoming data is compared to Xoff2. Detection of the special character sets the Xoff interrupt [IIR(4)] but does not halt transmission. The Xoff interrupt is cleared by a read of the IIR. The special character is transferred to the RX FIFO.

NOTE

It is possible for an Xon1 character to be recognized as an Xon Any character, which could cause an Xon2 character to be written to the RX FIFO.

Table 1. Software Flow Control Options EFR[3:0]

BIT 3	BIT 2	BIT 1	BIT 0	TX, RX SOFTWARE FLOW CONTROLS
0	0	X	X	No transmit flow control
1	0	X	X	Transmit Xon1, Xoff1
0	1	X	X	Transmit Xon2, Xoff2
1	1	X	X	Transmit Xon1, Xon2: Xoff1, Xoff2
X	X	0	0	No receive flow control
X	X	1	0	Receiver compares Xon1, Xoff1 X X 0 1
X	X	0	1	Receiver compares Xon2, Xoff2
1	0	1	1	Transmit Xon1, Xoff1 Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
0	1	1	1	Transmit Xon2, Xoff2 Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
1	1	1	1	Transmit Xon1, Xon2: Xoff1, Xoff2 Receiver compares Xon1 and Xon2: Xoff1 and Xoff2
0	0	1	1	No transmit flow control Receiver compares Xon1 and Xon2: Xoff1 and Xoff2

When software flow control operation is enabled, the TL16C752C device compares incoming data with Xoff1 and Xoff2 programmed characters (in certain cases Xoff1 and Xoff2 must be received sequentially). ^{When pairs of Xon and Xoff characters are programmed to occur sequentially, received Xon1 and Xoff1 characters will be written to the RX FIFO if the subsequent character is not Xon2 and Xoff2.} When an Xoff character is received, transmission is halted after completing transmission of the current character. Xoff character detection also sets IIR[4] and causes INT to go high (if enabled via IER[5]).

1. When pairs of Xon and Xoff characters are programmed to occur sequentially, received Xon1 and Xoff1 characters will be written to the RX FIFO if the subsequent character is not Xon2 and Xoff2.

To resume transmission an Xon1 and Xon2 character must be received (in certain cases Xon1 and Xon2 must be received sequentially). When the correct Xon characters are received IIR[4] is cleared and the Xoff interrupt disappears.

NOTE

If a parity, framing, or break error occurs while receiving a software flow control character, this character is treated as normal data and is written to the RCV FIFO.

Xoff1 and Xoff2 characters are transmitted when the RX FIFO has passed the programmed trigger level TCR[3:0].

Xon1 and Xon2 characters are transmitted when the RX FIFO reaches the trigger level programmed via TCR[7:4].

NOTE

If, after an Xoff character has been sent, software flow control is disabled, the UART transmits Xon characters automatically to enable normal transmission to proceed. A feature of the TL16C752C UART design is that if the software flow combination (EFR[3:0]) changes after an Xoff has been sent, the originally programmed Xon is automatically sent. If the RX FIFO is still above the trigger level, the newly programmed Xoff1 or Xoff2 is transmitted.

The transmission of Xoff and Xon follows the exact same protocol as transmission of an ordinary byte from the FIFO. This means that even if the word length is set to be 5, 6, or 7 characters, then the 5, 6, or 7 least significant bits of Xoff1, Xoff2 and Xon1, Xon2 are transmitted. The transmission of 5, 6, or 7 bits of a character is seldom done, but this functionality is included to maintain compatibility with earlier designs.

It is assumed that software flow control and hardware flow control are never enabled simultaneously. Figure 19 shows a software flow control example.

Figure 19. Software Flow Control Example

8.3.1.9 Interrupt Mode Operation

In interrupt mode (if any bit of IER[3:0] is 1), the processor is informed of the status of the receiver and transmitter by an interrupt signal, INT. Therefore, it is not necessary to continuously poll the line status register (LSR) to see if any interrupt needs to be serviced. Figure 20 shows interrupt mode operation.

Figure 20. Interrupt Mode Operation

8.3.1.10 Polled Mode Operation

In polled mode (IER[3:0] = 0000), the status of the receiver and transmitter can then be checked by polling the line status register (LSR). This mode is an alternative to the interrupt mode of operation where the status of the receiver and transmitter is automatically known by means of interrupts sent to the CPU. Figure 21 shows polled mode operation.

Figure 21. FIFO Polled Mode Operation

8.3.1.12 Programmable Baud Rate Generator

The TL16C752C UART contains a programmable baud generator that divides reference clock by a divisor in the range between 1 and (2¹⁶ − 1). The output frequency of the baud rate generator is 16× the baud rate. An additional divide-by-4 prescaler is also available and can be selected by MCR[7], as shown in the following. The formula for the divisor is:

Where

Figure 22 shows the internal prescaler and baud rate generator circuitry.

Figure 22. Prescaler and Baud Rate Generator Block Diagram

DLL and DLH must be written to to program the baud rate. DLL and DLH are the least significant and most significant byte of the baud rate divisor. If DLL and DLH are both 0, the UART is effectively disabled, because no baud clock is generated. The programmable baud rate generator is provided to select both the transmit and receive clock rates. Table 5 and Table 6 show the baud rate and divisor correlation for the crystal with frequency 1.8432 and 3.072 MHz, respectively.

Table 5. Baud Rates Using a 1.8432-MHz Crystal

DESIRED BAUD RATE	DIVISOR USED TO GENERATE 16× CLOCK	PERCENT ERROR DIFFERENCE BETWEEN DESIRED AND ACTUAL
50	2304
75	1536
110	1047	0.026
134.5	857	0.058
150	768
300	384
600	192
1200	96
1800	64
2000	58	0.69
2400	48
3600	32
4800	24
7200	16
9600	12
19200	6
38400	3
56000	2	2.86

Table 6. Baud Rates Using a 3.072-MHz Crystal

DESIRED BAUD RATE	DIVISOR USED TO GENERATE 16× CLOCK	PERCENT ERROR DIFFERENCE BETWEEN DESIRED AND ACTUAL
50	3840
75	2560
110	1745	0.026
134.5	1428	0.034
150	1280
300	640
600	320
1200	160
1800	107	0.312
2000	96
2400	80
3600	53	0.628
4800	40
7200	27	1.23
9600	20
19200	10
38400	5

Figure 23 shows the crystal clock circuit reference.

A. For crystal with fundamental frequency from 1 to 24 MHz

B. For input clock frequency higher than 24 MHz, the crystal is not allowed and the oscillator must be used, because the TL16C752C internal oscillator cell can only support the crystal frequency up to 24 MHz.

Figure 23. Typical Crystal Clock Circuits

8.4.1 DMA Signaling

There are two modes of DMA operation, DMA mode 0 or 1, selected by FCR[3].

In DMA mode 0 or FIFO disable (FCR[0] = 0), DMA occurs in single character transfers. In DMA mode 1, multicharacter (or block) DMA transfers are managed to relieve the processor for longer periods of time.

8.4.1.1 Single DMA Transfers (DMA Mode0 or FIFO Disable)

Transmitter: When empty, the TXRDY signal becomes active. TXRDY goes inactive after one character has been loaded into it.

Receiver: RXRDY is active when there is at least one character in the FIFO. It becomes inactive when the receiver is empty.

Figure 24 shows TXRDY and RXRDY in DMA mode 0 or FIFO disable.

Figure 24. TXRDY and RXRDY in DMA Mode 0 or FIFO Disable

8.4.1.2 Block DMA Transfers (DMA Mode 1)

Transmitter: TXRDY is active when a trigger level number of spaces are available. It becomes inactive when the FIFO is full.

Receiver: RXRDY becomes active when the trigger level has been reached or when a timeout interrupt occurs. It goes inactive when the FIFO is empty or an error in the RX FIFO is flagged by LSR(7).

Figure 25 shows TXRDY and RXRDY in DMA mode 1.

Figure 25. TXRDY and RXRDY in DMA Mode 1

8.4.2 Sleep Mode

Sleep mode is an enhanced feature of the TL16C752C UART. It is enabled when EFR[4], the enhanced functions bit, is set and when IER[4] is set. Sleep mode is entered when:

• The serial data input line, RX, is idle (see Break and Timeout Conditions).
• The TX FIFO and TX shift register are empty.
• There are no interrupts pending except THR and timeout interrupts.

Sleep mode is not entered if there is data in the RX FIFO.

In sleep mode, the UART clock and baud rate clock are stopped. Because most registers are clocked using these clocks, the power consumption is greatly reduced. The UART wakes up when any change is detected on the RX line, when there is any change in the state of the modem input pins, or if data is written to the TX FIFO.

8.5.1 Principals of Operation

Each register is selected using address lines A[0], A[1], A[2], and in some cases, bits from other registers. The programming combinations for register selection are shown in Figure 26.

NOTE:

MCR[7:5], FCR[5:4], and IER[7:4] can only be modified when EFR[4] is set.

Figure 26. Register Map – Read and Write Properties

Table 7 lists and describes the TL16C752C internal registers.

8.5.2 Receiver Holding Register (RHR)

The receiver section consists of the RHR and the receiver shift register (RSR). The RHR is actually a 64-byte FIFO. The RSR receives serial data from RX terminal. The data is converted to parallel data and moved to the RHR. The receiver section is controlled by the line control register. If the FIFO is disabled, location 0 of the FIFO is used to store the characters. If overflow occurs, characters are lost. The RHR also stores the error status bits associated with each character.

8.5.3 Transmit Holding Register (THR)

The transmitter section consists of the THR and the transmitter shift register (TSR). The transmit holding register is actually a 64-byte FIFO. The THR receives data and shifts it into the TSR where it is converted to serial data and moved out on the TX terminal. If the FIFO is disabled, location 0 of the FIFO is used to store the byte. Characters are lost if overflow occurs.

8.5.4 FIFO Control Register (FCR)

This is a write-only register which is used for enabling the FIFOs, clearing the FIFOs, setting transmitter and receiver trigger levels, and selecting the type of DMA signaling. Table 8 shows FIFO control register bit settings.

8.5.5 Line Control Register (LCR)

This register controls the data communication format. The word length, number of stop bits, and parity type are selected by writing the appropriate bits to the LCR. Table 9 shows line control register bit settings.

8.5.6 Line Status Register (LSR)

Table 10 shows line status register bit settings.

When the LSR is read, LSR[4:2] reflects the error bits [BI, FE, PE] of the character at the top of the RX FIFO (next character to be read). The LSR[4:2] registers do not physically exist, as the data read from the RX FIFO is output directly onto the output data-bus, DI[4:2], when the LSR is read. Therefore, errors in a character are identified by reading the LSR and then reading the RHR.

LSR[7] is set when there is an error anywhere in the RX FIFO and is cleared only when there are no more errors remaining in the FIFO.

8.5.7 Modem Control Register (MCR)

The MCR controls the interface with the modem, data set, or peripheral device that is emulating the modem. Table 11 shows modem control register bit settings.

8.5.8 Modem Status Register (MSR)

This 8-bit register provides information about the current state of the control lines from the modem, data set, or peripheral device to the processor. It also indicates when a control input from the modem changes state. Table 12 shows modem status register bit settings.

8.5.9 Interrupt Enable Register (IER)

The interrupt enable register (IER) enables each of the six types of interrupt, receiver error, RHR interrupt, THR interrupt, Xoff received, or CTS/RTS change of state from low to high. The INT output signal is activated in response to interrupt generation. Table 13 shows interrupt enable register bit settings.

8.5.10 Interrupt Identification Register (IIR)

The IIR is a read-only 8-bit register, which provides the source of the interrupt in a prioritized manner. Table 14 shows interrupt identification register bit settings.

The interrupt priority list is illustrated in Table 15.

8.5.11 Enhanced Feature Register (EFR)

This 8-bit register enables or disables the enhanced features of the UART. Table 16 shows the enhanced feature register bit settings.

8.5.12 Divisor Latches (DLL, DLH)

Two 8-bit registers store the 16-bit divisor for generation of the baud clock in the baud rate generator. DLH, stores the most significant part of the divisor. DLL stores the least significant part of the division.

DLL and DLH can only be written to before sleep mode is enabled (that is, before IER[4] is set).

8.5.13 Transmission Control Register (TCR)

This 8-bit register is used to store the receive FIFO threshold levels to start or stop transmission during hardware or software flow control. Table 17 shows transmission control register bit settings.

TCR trigger levels are available from 0 to 60 bytes with a granularity of four.

TCR can be written to only when EFR[4] = 1 and MCR[6] = 1. The programmer must program the TCR such that TCR[3:0] > TCR[7:4]. There is no built-in hardware check to make sure this condition is met. Also, the TCR must be programmed with this condition before Auto-RTS or software flow control is enabled to avoid spurious operation of the device.

8.5.14 Trigger Level Register (TLR)

This 8-bit register is used to store the transmit and received FIFO trigger levels used for DMA and interrupt generation. Trigger levels from 4 to 60 can be programmed with a granularity of 4. Table 18 shows trigger level register bit settings.

TLR can be written to only when EFR[4] = 1 and MCR[6] = 1. If TLR[3:0] or TLR[7:4] are 0, then the selectable trigger levels via the FIFO control register (FCR) are used for the transmit and receive FIFO trigger levels. Trigger levels from 4 to 60 bytes are available with a granularity of 4. The TLR should be programmed for N / 4, where N is the desired trigger level.

8.5.15 FIFO Ready Register

The FIFO ready register provides realtime status of the transmit and receive FIFOs of both channels. Table 19 shows the FIFO ready register bit settings. The trigger level mentioned in Table 19 refers to the setting in either FCR (when TLR value is 0), or TLR (when it has a nonzero value).

The FIFORdy register is a read only register and can be accessed when any of the two UARTs are selected. CSA or CSB = 0, MCR[2] (FIFORdy Enable) is a logic 1, and loopback is disabled. Its address is 111.

8.5.16 Alternate Function Register (AFR)

The AFR is used to enable some extra functionality beyond the capabilities of the original TL16C752B. The first of these is a concurrent write mode, which can be useful in more expediently setting up all four UART channels. The second addition is the IrDA mode, which supports Standard IrDA (SIR) mode with baud rates from 2400 to 115.2 bps. The third addition is support for RS-485 bus drivers or transceivers by providing an output pin (DTRx) per channel, which is timed to keep the RS-485 driver enabled as long as transmit data is pending.

The AFR is located at A[2:0] = 010 when LCR[7:5] = 100.

8.5.17 RS-485 Mode

The RS-485 mode is intended to simplify the interface between the UART channel and an RS-485 driver or transceiver. When enabled by setting 485EN, the DTRx output goes high one bit time before the first stop bit of the first data byte being sent, and remains high as long as there is pending data in the TSR or THR (xmt fifo). After both are empty (after the last stop bit of the last data byte), the DTRx output stays high for a programmable delay of 0 to 15 bit times, as set by DLY[2:0]. This helps preserve data integrity over long signal lines. This is illustrated in the following.

Often RS-485 packets are relatively short and the entire packet can fit within the 64 byte xmt fifo. In this case, it goes empty when the TSR goes empty. But in cases where a larger block needs to be sent, it is advantageous to reload the xmt fifo as soon as it is depleted. Otherwise, the transmission stalls while waiting for the xmt fifo to be reloaded, which varies with processor load. In this case, it is best to also set 485LG (large block), which causes the transmit interrupt to occur wither when the THR becomes empty (if the xmt fifo level was not above the threshold), or when the xmt fifo threshold is crossed. The reloading of the xmt fifo occurs while some data is being shifted out, eliminating fifo underrun. If desired, when the last bytes of a current transmission are being loaded in the xmt fifo, 485LG can be cleared before the load and the transmit interrupt occurs on the TSR going empty.

A. Waveforms are not shown to scale, as the WR THR pulses typically are less than 100 ns, where the TX waveform varies with baud rate but is typically in the microsecond range.

Figure 27. DTRx and Transmit Data Relationship

Figure 28. RS-485 Application Example 1

Figure 29. RS-485 Application Example 2

8.5.18 IrDA Overview

Figure 30. IrDA Mode

The IrDA defines several protocols for sending and receiving serial infrared data, including rates of 115.2 kbps, 0.576 Mbps, 1.152 Mbps, and 4 Mbps. The low rate of 115.2 kbps was specified first and the others must maintain downward compatibility with it. At the 115.2 kbps rate, the protocol implemented in the hardware is fairly simple. It primarily defines a serial infrared data word to be surrounded by a start bit equal to 0 and a stop bit equal to 1. Individual bits are encoded or decoded the same whether they are start, data, or stop bits. The IrDA engine in the TL16C752C device only evaluates single bits and follows the 115.2-kbps protocol. The 115.2-kbps rate is a maximum rate. When both ends of the transfer are setup to a lower but matching speed, the protocol still works. The clock used to code or sample the data is 16 times the baud rate, or 1.843-MHz maximum. To code a 1, no pulse is sent or received for 1-bit time period, or 16 clock cycles. To code a 0, one pulse is sent or received within a 1-bit time period, or 16 clock cycles. The pulse must be at least 1.6-μs wide and 3 clock cycles long at 1.843 MHz. At lower baud rates the pulse can be 1.6 μs wide or as long as 3 clock cycles. The transmitter output, TX, is intended to drive a LED circuit to generate an infrared pulse. The LED circuits work on positive pulses. A terminal circuit is expected to create the receiver input, RX. Most, but not all, PIN circuits have inversion and generate negative pulses from the detected infrared light. Their output is normally high. The TL16C752C device can decode either negative or positive pulses on RX.

8.5.19 IrDA Encoder Function

Serial data from a UART is encoded to transmit data to the optoelectronics. While the serial data input to this block (Int_TX) is high, the output (TX) is always low, and the counter used to form a pulse on TX is continuously cleared. After Int_TX resets to 0, TX rises on the falling edge of the 7^th 16XCLK. On the falling edge of the 10^th 16XCLK pulse, TX falls, creating a 3-clock-wide pulse. While Int_TX stays low, a pulse is transmitted during the seventh to tenth clocks of each 16-clock bit cycle.

Figure 31. IrDA-SIR Encoding Scheme – Detailed Timing Diagram

Figure 32. Encoding Scheme – Macro View

After reset, Int_RX is high and the 4-bit counter is cleared. When a falling edge is detected on RX, Int_RX falls on the next rising edge of 16XCLK with sufficient setup time. Int_RX stays low for 16 cycles (16XCLK) and then returns to high as required by the IrDA specification. As long as no pulses (falling edges) are detected on RX, Int_RX remains high.

Figure 33. IrDA-SIR Decoding Scheme – Detailed Timing Diagram

Figure 34. IrDA-SIR Decoding Scheme – Macro View

It is possible for jitter or slight frequency differences to cause the next falling edge on RX to be missed for one 16XCLK cycle. In that case, a 1-clock-wide pulse appears on Int_RX between consecutive 0s. It is important for the UART to strobe Int_RX in the middle of the bit time to avoid latching this 1-clock-wide pulse. The TL16C550C UART already strobes incoming serial data at the proper time. Otherwise, note that data is required to be framed by a leading 0 and a trailing 1. The falling edge of that first 0 on Int_RX synchronizes the read strobe. The strobe occurs on the 8^th 16XCLK pulse after the Int_RX falling edge and once every 16 cycles thereafter until the stop bit occurs.

Figure 35. Timing Causing 1-Clock-Wide Pulse Between Consecutive Ones

Figure 36. Recommended Strobing for Decoded Data

The TL16C752C device can decode positive pulses on RX. The timing is different, but the variation is invisible to the UART. The decoder, which works from the falling edge, now recognizes a 0 on the trailing edge of the pulse rather than on the leading edge. As long as the pulse duration is fairly constant, as defined by the specification, the trailing edges should also be 16 clock cycles apart and data can readily be decoded. The 0 appears on Int_RX after the pulse rather than at the start of it.

Figure 37. Positive RX Pulse Decode – Detailed View

Figure 38. Positive RX Pulse Decode – Macro View