SLLSEQ9A October   2015  – February 2016 TL16C752CI-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configurations and Function
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Functional Description
        1. 8.3.1.1  Trigger Levels
        2. 8.3.1.2  Hardware Flow Control
        3. 8.3.1.3  Auto-RTS
        4. 8.3.1.4  Auto-CTS
        5. 8.3.1.5  Software Flow Control
        6. 8.3.1.6  Software Flow Control Example
        7. 8.3.1.7  Reset
        8. 8.3.1.8  Interrupts
        9. 8.3.1.9  Interrupt Mode Operation
        10. 8.3.1.10 Polled Mode Operation
        11. 8.3.1.11 Break and Timeout Conditions
        12. 8.3.1.12 Programmable Baud Rate Generator
    4. 8.4 Device Functional Modes
      1. 8.4.1 DMA Signaling
        1. 8.4.1.1 Single DMA Transfers (DMA Mode0 or FIFO Disable)
        2. 8.4.1.2 Block DMA Transfers (DMA Mode 1)
      2. 8.4.2 Sleep Mode
    5. 8.5 Register Maps
      1. 8.5.1  Principals of Operation
      2. 8.5.2  Receiver Holding Register (RHR)
      3. 8.5.3  Transmit Holding Register (THR)
      4. 8.5.4  FIFO Control Register (FCR)
      5. 8.5.5  Line Control Register (LCR)
      6. 8.5.6  Line Status Register (LSR)
      7. 8.5.7  Modem Control Register (MCR)
      8. 8.5.8  Modem Status Register (MSR)
      9. 8.5.9  Interrupt Enable Register (IER)
      10. 8.5.10 Interrupt Identification Register (IIR)
      11. 8.5.11 Enhanced Feature Register (EFR)
      12. 8.5.12 Divisor Latches (DLL, DLH)
      13. 8.5.13 Transmission Control Register (TCR)
      14. 8.5.14 Trigger Level Register (TLR)
      15. 8.5.15 FIFO Ready Register
      16. 8.5.16 Alternate Function Register (AFR)
      17. 8.5.17 RS-485 Mode
      18. 8.5.18 IrDA Overview
      19. 8.5.19 IrDA Encoder Function
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Community Resource
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Q100 Automotive Qualified
  • SC16C752B and XR16M752 Pin Compatible With Additional Enhancements
  • Support 1.8-V, 2.5-V, 3.3-V, or 5-V Supply
  • Characterized for Operation from –40°C to +105°C
  • Supports up to:
    • 48-MHz Oscillator Input Clock (3 Mbps) for 5-V Operation
    • 32-MHz Oscillator Input Clock (2 Mbps) for 3.3-V Operation
    • 24-MHz Input Clock (1.5 Mbps) for 2.5-V Operation
    • 16-MHz Input Clock (1 Mbps) for 1.8-V Operation
  • 64-Byte Transmit/Receive FIFO
  • Software-Selectable Baud-Rate Generator
  • Programmable and Selectable Transmit and Receive FIFO Trigger Levels for DMA, Interrupt Generation, and Software or Hardware Flow Control
  • Software/Hardware Flow Control
    • Programmable Xon and Xoff Characters With Optional Xon Any Character
    • Programmable Auto-RTS and Auto-CTS-Modem Control Functions (CTS, RTS, DSR, DTR, RI, and CD)
  • DMA Signaling Capability for Both Received and Transmitted Data on PN Package
  • RS-485 Mode Support
  • Infrared Data Association (IrDA) Capability
  • Programmable Sleep Mode
  • Programmable Serial Interface Characteristics
    • 5, 6, 7, or 8-Bit Characters With 1, 1.5, or 2 Stop Bit Generation
    • Even, Odd, or No Parity Bit Generation and Detection
  • False Start Bit and Line Break Detection
  • Internal Test and Loopback Capabilities

2 Applications

  • GPS Systems
  • Ethernet Network Routers
  • Infrared Transceivers
  • Domestic Applications
  • Portable Applications
  • Factory Automation and Process Control

3 Description

The TL16C752CI-Q1 is a dual universal asynchronous receiver transmitter (UART) with 64-byte FIFOs, automatic hardware and software flow control, and data rates up to 3 Mbps. The device offers enhanced features. It has a transmission Character control register (TCR) that stores received FIFO threshold level to start or stop transmission during hardware and software flow control.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
TL16C752CI-Q1 TQFP (48) 7.00 mm × 7.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Block Diagram

TL16C752CI-Q1 fbd_lls646.gif