SLLSEN8C September   2015  – June 2017 TL16C752D

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configurations and Function
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Functional Description
        1. 8.3.1.1  Trigger Levels
        2. 8.3.1.2  Hardware Flow Control
        3. 8.3.1.3  Auto-RTS
        4. 8.3.1.4  Auto-CTS
        5. 8.3.1.5  Software Flow Control
        6. 8.3.1.6  Software Flow Control Example
        7. 8.3.1.7  Reset
        8. 8.3.1.8  Interrupts
        9. 8.3.1.9  Interrupt Mode Operation
        10. 8.3.1.10 Polled Mode Operation
        11. 8.3.1.11 Break and Timeout Conditions
        12. 8.3.1.12 Programmable Baud Rate Generator
    4. 8.4 Device Functional Modes
      1. 8.4.1 DMA Signaling
        1. 8.4.1.1 Single DMA Transfers (DMA Mode0 or FIFO Disable)
        2. 8.4.1.2 Block DMA Transfers (DMA Mode 1)
      2. 8.4.2 Sleep Mode
    5. 8.5 Register Maps
      1. 8.5.1  Principals of Operation
      2. 8.5.2  Receiver Holding Register (RHR)
      3. 8.5.3  Transmit Holding Register (THR)
      4. 8.5.4  FIFO Control Register (FCR)
      5. 8.5.5  Line Control Register (LCR)
      6. 8.5.6  Line Status Register (LSR)
      7. 8.5.7  Modem Control Register (MCR)
      8. 8.5.8  Modem Status Register (MSR)
      9. 8.5.9  Interrupt Enable Register (IER)
      10. 8.5.10 Interrupt Identification Register (IIR)
      11. 8.5.11 Enhanced Feature Register (EFR)
      12. 8.5.12 Divisor Latches (DLL, DLH)
      13. 8.5.13 Transmission Control Register (TCR)
      14. 8.5.14 Trigger Level Register (TLR)
      15. 8.5.15 FIFO Ready Register
      16. 8.5.16 Alternate Function Register (AFR)
      17. 8.5.17 RS-485 Mode
      18. 8.5.18 IrDA Overview
      19. 8.5.19 IrDA Encoder Function
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Community Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Description (continued)

The two UARTs share only the data bus interface and clock source, otherwise they operate independently. Another name for the UART function is asynchronous communications element (ACE), and these terms are used interchangeably. The bulk of this document describes the behavior of each ACE, with the understanding that two such devices are incorporated into the TL16C752D device.