SLLS890C August   2008  – April 2024 TL28L92

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Description
  4. 3Pin Configurations and Functions
  5. 4Electrical Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 Static Characteristics for 5V Operation
    3. 4.3 Static Characteristics for 3.3V Operation
    4. 4.4 Dynamic Characteristics for 5V Operation
    5. 4.5 Dynamic Characteristics for 3.3V Operation
    6. 4.6 Typical Performance
    7. 4.7 Timing Diagrams
    8. 4.8 Test Information
  6. 5Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
      1. 5.3.1 Data Bus Buffer
      2. 5.3.2 Operation Control
      3. 5.3.3 Interrupt Control
      4. 5.3.4 FIFO Configuration
      5. 5.3.5 68xxx Mode
      6. 5.3.6 Timing Circuits
        1. 5.3.6.1  Crystal Clock
        2. 5.3.6.2  Baud Rate Generator
        3. 5.3.6.3  Counter/Timer
        4. 5.3.6.4  Timer Mode
        5. 5.3.6.5  Counter Mode
        6. 5.3.6.6  Time-Out Mode
        7. 5.3.6.7  Time-Out Mode Caution
        8. 5.3.6.8  Communications Channels A and B
        9. 5.3.6.9  Input Port
        10. 5.3.6.10 Output Port
      7. 5.3.7 Operation
        1. 5.3.7.1 Transmitter
        2. 5.3.7.2 Receiver
        3. 5.3.7.3 Transmitter Reset and Disable
        4. 5.3.7.4 Receiver FIFO
        5. 5.3.7.5 Receiver Status Bits
        6. 5.3.7.6 Receiver Reset and Disable
        7. 5.3.7.7 Watchdog
        8. 5.3.7.8 Receiver Time-Out Mode
        9. 5.3.7.9 Time-Out Mode Caution
  7. 6Programming
    1. 6.1 Register Overview
    2. 6.2 Condensed Register Bit Formats
    3. 6.3 Register Descriptions
      1. 6.3.1  Mode Registers
        1. 6.3.1.1 Mode Register 0 Channel A (MR0A)
        2. 6.3.1.2 Mode Register 1 Channel A (MR1A)
        3. 6.3.1.3 Mode Register 2 Channel A (MR2A)
        4. 6.3.1.4 Mode Register 0 Channel B (MR0B)
        5. 6.3.1.5 Mode Register 1 Channel B (MR1B)
        6. 6.3.1.6 Mode Register 2 Channel B (MR2B)
      2. 6.3.2  Clock Select Registers
        1. 6.3.2.1 Clock Select Register Channel A (CSRA)
        2. 6.3.2.2 Clock Select Register Channel B (CSRB)
      3. 6.3.3  Command Registers
        1. 6.3.3.1 Command Register Channel A (CRA)
        2. 6.3.3.2 Command Register Channel B (CRB)
      4. 6.3.4  Status Registers
        1. 6.3.4.1 Status Register Channel A (SRA)
        2. 6.3.4.2 Status Register Channel B (SRB)
      5. 6.3.5  Output Configuration Control Register (OPCR)
      6. 6.3.6  Set Output Port Bits Register (SOPR)
      7. 6.3.7  Reset Output Port Bits Register (ROPR)
      8. 6.3.8  Output Port Register (OPR)
      9. 6.3.9  Auxiliary Control Register (ACR)
      10. 6.3.10 Input Port Change Register (IPCR)
      11. 6.3.11 Interrupt Status Register (ISR)
      12. 6.3.12 Interrupt Mask Register (IMR)
      13. 6.3.13 Interrupt Vector Register (IVR; 68xxx Mode) or General Purpose Register (GP; 80xxx Mode)
      14. 6.3.14 Counter and Timer Registers
    4. 6.4 Output Port Notes
    5. 6.5 CTS, RTS, CTS Enable Tx Signals
  8. 7Device and Documentation Support
    1. 7.1 Receiving Notification of Documentation Updates
    2. 7.2 Support Resources
    3. 7.3 Trademarks
    4. 7.4 Electrostatic Discharge Caution
    5. 7.5 Glossary
  9. 8Revision History
  10. 9Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.1.1 Mode Register 0 Channel A (MR0A)

Table 6-20 Mode Register 0 Channel A (MR0A) (Address 0x0) Bit Allocation(1)
76543210
RxWATCHDOGRxINT[2]TxINT[1:0]FIFOSIZEBAUDRATE EXTENDED IITEST2BAUDRATE EXTENDED I
(1) MR0 is accessed by setting the MR pointer to logic 0 via the command register command B.
Table 6-21 Mode Register 0 Channel A (MR0A) (Address 0x0) Bit Description
BIT(S)SYMBOLDESCRIPTION
7RxWATCHDOGThis bit controls the receiver watchdog timer.
0 = disable
1 = enable
When enabled, the watchdog timer will generate a receiver interrupt if the receiver FIFO has not been accessed within 64 bit times of the receiver 1× clock. The watchdog timer is used to alert the control processor that data is in the Rx FIFO that has not been read. This situation will occur when the byte count of the last part of a message is not large enough to generate an interrupt. The watchdog timer presents itself as a receiver interrupt with the RxRDY bit set in SR and ISR.
6RxINT[2]Bit 2 of receiver FIFO interrupt level. This bit along with bit 6 of MR1 sets the fill level of the FIFO that generates the receiver interrupt. Note that this control is split between MR0 and MR1. This is for backward compatibility to the SC2692. For the receiver these bits control the number of FIFO positions filled when the receiver will attempt to interrupt. After the reset the receiver FIFO is empty. The default setting of these bits cause the receiver to attempt to interrupt when it has one or more bytes in it; see Table 6-22
5 and 4TxINT[1:0]Transmitter interrupt fill level. For the transmitter these bits control the number of FIFO positions empty when the receiver will attempt to interrupt; see Table 6-23. After the reset the transmit FIFO has 8 bytes empty. It will then attempt to interrupt as soon as the transmitter is enabled. The default setting (TxINT[1:0] = 00) condition the transmitter to attempt to interrupt only when it is completely empty. As soon as one byte is loaded, it is no longer empty and hence will withdraw its interrupt request.
3FIFOSIZEFIFO size for channel A and channel B. Selects the FIFO depth at 8-byte or 16-byte.
0 = 8 bytes
1 = 16 bytes
2BAUDRATE EXTENDED IBits MR0[2:0] are used to select one of the six baud rate groups. See Table 6-32 for the group organization.
1TEST2000 = Normal mode
0BAUDRATE EXTENDED II001 = Extended mode I
100 = Extended mode II
Other combinations of MR0[2:0] should not be used.
Table 6-22 Receiver FIFO Interrupt Fill Level(1)
RxINT[2:1] (BITS MR0[6] AND MR1[6])INTERRUPT CONDITION
FIFOSIZE = 0 (8 bytes)
001 or more bytes in FIFO (RxRDY)
013 or more bytes in FIFO
106 or more bytes in FIFO
118 bytes in FIFO (RxFULL)
FIFOSIZE = 1 (16 bytes)
001 or more bytes in FIFO (RxRDY)
018 or more bytes in FIFO
1012 or more bytes in FIFO
1116 bytes in FIFO (RxFULL)
(1) Interrupt fill level must be set when the transmit and receive FIFOs are empty, otherwise the new level takes effect only after a read or a write to the FIFO.
Table 6-23 Transmitter FIFO Interrupt Fill Level(1)
TxINT[2:1] (BITS MR0[6] AND MR1[6])INTERRUPT CONDITION
FIFOSIZE = 0 (8 bytes)
008 bytes empty (TxEMPTY)
014 or more bytes empty
106 or more bytes empty
111 or more bytes empty (TxRDY)
FIFOSIZE = 1 (16 bytes)
0016 bytes empty (TxEMPTY)
018 or more bytes empty
1012 or more bytes empty
111 or more bytes empty (TxRDY)
(1) Interrupt fill level must be set when the transmit and receive FIFOs are empty, otherwise the new level takes effect only after a read or a write to the FIFO.