SLLS890C August   2008  – April 2024 TL28L92

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Description
  4. 3Pin Configurations and Functions
  5. 4Electrical Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 Static Characteristics for 5V Operation
    3. 4.3 Static Characteristics for 3.3V Operation
    4. 4.4 Dynamic Characteristics for 5V Operation
    5. 4.5 Dynamic Characteristics for 3.3V Operation
    6. 4.6 Typical Performance
    7. 4.7 Timing Diagrams
    8. 4.8 Test Information
  6. 5Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
      1. 5.3.1 Data Bus Buffer
      2. 5.3.2 Operation Control
      3. 5.3.3 Interrupt Control
      4. 5.3.4 FIFO Configuration
      5. 5.3.5 68xxx Mode
      6. 5.3.6 Timing Circuits
        1. 5.3.6.1  Crystal Clock
        2. 5.3.6.2  Baud Rate Generator
        3. 5.3.6.3  Counter/Timer
        4. 5.3.6.4  Timer Mode
        5. 5.3.6.5  Counter Mode
        6. 5.3.6.6  Time-Out Mode
        7. 5.3.6.7  Time-Out Mode Caution
        8. 5.3.6.8  Communications Channels A and B
        9. 5.3.6.9  Input Port
        10. 5.3.6.10 Output Port
      7. 5.3.7 Operation
        1. 5.3.7.1 Transmitter
        2. 5.3.7.2 Receiver
        3. 5.3.7.3 Transmitter Reset and Disable
        4. 5.3.7.4 Receiver FIFO
        5. 5.3.7.5 Receiver Status Bits
        6. 5.3.7.6 Receiver Reset and Disable
        7. 5.3.7.7 Watchdog
        8. 5.3.7.8 Receiver Time-Out Mode
        9. 5.3.7.9 Time-Out Mode Caution
  7. 6Programming
    1. 6.1 Register Overview
    2. 6.2 Condensed Register Bit Formats
    3. 6.3 Register Descriptions
      1. 6.3.1  Mode Registers
        1. 6.3.1.1 Mode Register 0 Channel A (MR0A)
        2. 6.3.1.2 Mode Register 1 Channel A (MR1A)
        3. 6.3.1.3 Mode Register 2 Channel A (MR2A)
        4. 6.3.1.4 Mode Register 0 Channel B (MR0B)
        5. 6.3.1.5 Mode Register 1 Channel B (MR1B)
        6. 6.3.1.6 Mode Register 2 Channel B (MR2B)
      2. 6.3.2  Clock Select Registers
        1. 6.3.2.1 Clock Select Register Channel A (CSRA)
        2. 6.3.2.2 Clock Select Register Channel B (CSRB)
      3. 6.3.3  Command Registers
        1. 6.3.3.1 Command Register Channel A (CRA)
        2. 6.3.3.2 Command Register Channel B (CRB)
      4. 6.3.4  Status Registers
        1. 6.3.4.1 Status Register Channel A (SRA)
        2. 6.3.4.2 Status Register Channel B (SRB)
      5. 6.3.5  Output Configuration Control Register (OPCR)
      6. 6.3.6  Set Output Port Bits Register (SOPR)
      7. 6.3.7  Reset Output Port Bits Register (ROPR)
      8. 6.3.8  Output Port Register (OPR)
      9. 6.3.9  Auxiliary Control Register (ACR)
      10. 6.3.10 Input Port Change Register (IPCR)
      11. 6.3.11 Interrupt Status Register (ISR)
      12. 6.3.12 Interrupt Mask Register (IMR)
      13. 6.3.13 Interrupt Vector Register (IVR; 68xxx Mode) or General Purpose Register (GP; 80xxx Mode)
      14. 6.3.14 Counter and Timer Registers
    4. 6.4 Output Port Notes
    5. 6.5 CTS, RTS, CTS Enable Tx Signals
  8. 7Device and Documentation Support
    1. 7.1 Receiving Notification of Documentation Updates
    2. 7.2 Support Resources
    3. 7.3 Trademarks
    4. 7.4 Electrostatic Discharge Caution
    5. 7.5 Glossary
  9. 8Revision History
  10. 9Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.2.1 Clock Select Register Channel A (CSRA)

Table 6-31 Clock Select Register Channel A (CSRA) (Address 0x1) Bit Description
BIT(S)SYMBOLDESCRIPTION
7 to 4–Receiver clock select. The baud rate clock for the channel A receiver is as shown in Table 6-32, except as follows:
1110 = IP4 – 16×
1111 = IP4 – 1×
The receiver clock is always a 16× clock except for CSRA[7:4] = 1111
3 to 0–Transmitter clock select. The baud rate clock for the channel A transmitter is as shown in Table 6-32, except as follows:
1110 = IP3 – 16×
1111 = IP3 – 1×
The transmitter clock is always a 16× clock except for CSRA[3:0] = 1111
Table 6-32 Baud Rate (Based on a 3.6864 MHz Crystal Clock)(1)
CSR[7:4]MR0[0] = 0 (NORMAL MODE)MR0[0] = 1 (EXTENDED MODE I)MR0[2] = 1 (EXTENDED MODE II)
CSR[3:0]ACR[7] = 0ACR[7] = 1ACR[7] = 0ACR[7] = 1ACR[7] = 0ACR[7] = 1
000050753004504,8007,200
0001110110110110880880
0010134.5134.5134.5134.51,0761,076
0011200150120090019.20014.400
01003003001800180028.80028.800
01016006003600360057.60057.600
01101,2001,2007,2007,200115,200115,200
01111,0502,0001,0502,0001,0502,000
10002,4002,40014,40014,40057,60057,600
10014,8004,80028,80028,8004,8004,800
10107,2001,8007,2001,80057,60014,400
10119,6009,60057,60057,6009,6009,600
110038,40019,200230,400115,20038,40019,200
1101TimerTimerTimerTimerTimerTimer
(1) See Table 6-33 for bit rate characteristics.
Table 6-33 Bit Rate Generator Characteristics(1)(2)
NORMAL RATE (BAUD)ACTUAL 16× CLOCK (kHz)ERROR (%)
500.80
751.20
1101.759–0.069
134.52.1530.059
1502.4 00
2003.20
3004.80
6009.60
105016.756–0.260
120019.20
180028.80
200032.0560.175
240038.40
480076.80
7200115.20
9600153.60
19200307.20
38400614.40
(1) Crystal or clock = 3.6864 MHz.
(2) Duty cycle of 16× clock is 50% ± 1%.