SLLS890C August   2008  – April 2024 TL28L92

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Description
  4. 3Pin Configurations and Functions
  5. 4Electrical Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 Static Characteristics for 5V Operation
    3. 4.3 Static Characteristics for 3.3V Operation
    4. 4.4 Dynamic Characteristics for 5V Operation
    5. 4.5 Dynamic Characteristics for 3.3V Operation
    6. 4.6 Typical Performance
    7. 4.7 Timing Diagrams
    8. 4.8 Test Information
  6. 5Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
      1. 5.3.1 Data Bus Buffer
      2. 5.3.2 Operation Control
      3. 5.3.3 Interrupt Control
      4. 5.3.4 FIFO Configuration
      5. 5.3.5 68xxx Mode
      6. 5.3.6 Timing Circuits
        1. 5.3.6.1  Crystal Clock
        2. 5.3.6.2  Baud Rate Generator
        3. 5.3.6.3  Counter/Timer
        4. 5.3.6.4  Timer Mode
        5. 5.3.6.5  Counter Mode
        6. 5.3.6.6  Time-Out Mode
        7. 5.3.6.7  Time-Out Mode Caution
        8. 5.3.6.8  Communications Channels A and B
        9. 5.3.6.9  Input Port
        10. 5.3.6.10 Output Port
      7. 5.3.7 Operation
        1. 5.3.7.1 Transmitter
        2. 5.3.7.2 Receiver
        3. 5.3.7.3 Transmitter Reset and Disable
        4. 5.3.7.4 Receiver FIFO
        5. 5.3.7.5 Receiver Status Bits
        6. 5.3.7.6 Receiver Reset and Disable
        7. 5.3.7.7 Watchdog
        8. 5.3.7.8 Receiver Time-Out Mode
        9. 5.3.7.9 Time-Out Mode Caution
  7. 6Programming
    1. 6.1 Register Overview
    2. 6.2 Condensed Register Bit Formats
    3. 6.3 Register Descriptions
      1. 6.3.1  Mode Registers
        1. 6.3.1.1 Mode Register 0 Channel A (MR0A)
        2. 6.3.1.2 Mode Register 1 Channel A (MR1A)
        3. 6.3.1.3 Mode Register 2 Channel A (MR2A)
        4. 6.3.1.4 Mode Register 0 Channel B (MR0B)
        5. 6.3.1.5 Mode Register 1 Channel B (MR1B)
        6. 6.3.1.6 Mode Register 2 Channel B (MR2B)
      2. 6.3.2  Clock Select Registers
        1. 6.3.2.1 Clock Select Register Channel A (CSRA)
        2. 6.3.2.2 Clock Select Register Channel B (CSRB)
      3. 6.3.3  Command Registers
        1. 6.3.3.1 Command Register Channel A (CRA)
        2. 6.3.3.2 Command Register Channel B (CRB)
      4. 6.3.4  Status Registers
        1. 6.3.4.1 Status Register Channel A (SRA)
        2. 6.3.4.2 Status Register Channel B (SRB)
      5. 6.3.5  Output Configuration Control Register (OPCR)
      6. 6.3.6  Set Output Port Bits Register (SOPR)
      7. 6.3.7  Reset Output Port Bits Register (ROPR)
      8. 6.3.8  Output Port Register (OPR)
      9. 6.3.9  Auxiliary Control Register (ACR)
      10. 6.3.10 Input Port Change Register (IPCR)
      11. 6.3.11 Interrupt Status Register (ISR)
      12. 6.3.12 Interrupt Mask Register (IMR)
      13. 6.3.13 Interrupt Vector Register (IVR; 68xxx Mode) or General Purpose Register (GP; 80xxx Mode)
      14. 6.3.14 Counter and Timer Registers
    4. 6.4 Output Port Notes
    5. 6.5 CTS, RTS, CTS Enable Tx Signals
  8. 7Device and Documentation Support
    1. 7.1 Receiving Notification of Documentation Updates
    2. 7.2 Support Resources
    3. 7.3 Trademarks
    4. 7.4 Electrostatic Discharge Caution
    5. 7.5 Glossary
  9. 8Revision History
  10. 9Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Pin Configurations and Functions

Figure 3-1 80xxx Mode FR (QFP) Package
(Top View)
Table 3-1 Pin Functions for 80xxx Interface
PINS TYPE DESCRIPTION
NAME QFP (FR)
PIN NO.
A0, A1,
A2, A3		 40, 42,
44, 1		 I Address inputs: Select the DUART internal registers and ports for read/write operations.
CEN 33 I Chip enable: active LOW input signal. When LOW, data transfers between the CPU and the DUART are enabled on D0 to D7 as controlled by the WRN, RDN and A0 to A3 inputs. When HIGH, places the D0 to D7 lines in the 3-state condition.
D0, D1,
D2, D3,
D4, D5,
D6, D7		 22, 12,
21,13,
20, 14,
19, 15		 I/O Data bus: Bidirectional 3-state data bus used to transfer commands, data and status between the DUART and the CPU. D0 is the least significant bit.
GND 16, 17 Pwr Ground
IP0 2 I Input 0: General purpose input or channel A clear to send active LOW input (CTSAN).
IP1 43 I Input 1: General purpose input or channel B clear to send active LOW input (CTSBN).
IP2 34 I Input 2: General-purpose input or counter/timer external clock input.
IP3 41 I Input 3: General purpose input or channel A transmitter external clock input (TxCA). When the external clock is used by the transmitter, the transmitted data is clocked on the falling edge of the clock.
IP4 37 I Input 4: General purpose input or channel A receiver external clock input (RxCA). When the external clock is used by the receiver, the received data is sampled on the rising edge of the clock.
IP5 36 I Input 5: General purpose input or channel B transmitter external clock input (TxCB). When the external clock is used by the transmitter, the transmitted data is clocked on the falling edge of the clock.
IP6 35 I Input 6: General purpose input or channel B receiver external clock input (RxCB). When the external clock is used by the receiver, the received data is sampled on the rising edge of the clock.
I/M 11 I Bus configuration: When HIGH or not connected configures the bus interface to the conditions shown in this table.
INTRN 18 O Interrupt request: Active LOW, open-drain, output which signals the CPU that one or more of the eight maskable interrupting conditions are true. This pin requires a pull-up device.
N.C. 23 – Not connected
OP0 27 O Output 0: General purpose output or channel A request to send (RTSAN, active LOW). Can be deactivated automatically on receive or transmit.
OP1 7 O Output 1: General-purpose output or channel B request to send (RTSBN, active LOW). Can be deactivated automatically on receive or transmit.
OP2 26 O Output 2: General purpose output, or channel A transmitter 1× or 16× clock output, or channel A receiver 1× clock output.
OP3 8 O Output 3: General purpose output or open-drain, active LOW counter/timer output or channel B transmitter 1× clock output, or channel B receiver 1× clock output.
OP4 25 O Output 4: General purpose output or channel A open-drain, active LOW, RxA interrupt ISR[1] output.
OP5 9 O Output 5: General-purpose output or channel B open-drain, active LOW, RxB interrupt ISR[5] output.
OP6 24 O Output 6: General purpose output or channel A open-drain, active LOW, TxA interrupt ISR[0] output.
OP7 10 O Output 7: General-purpose output, or channel B open-drain, active LOW, TxB interrupt ISR[4] output.
RDN 4 I Read strobe: When LOW and CEN is also LOW, causes the contents of the addressed register to be presented on the data bus. The read cycle begins on the falling edge of RDN.
RESET 32 I Reset: A HIGH level clears internal registers (SRA, SRB, IMR, ISR, OPR and OPCR), puts OP0 to OP7 in the HIGH state, stops the counter/timer, and puts channels A and B in the inactive state, with the TxDA and TxDB outputs in the mark (HIGH) state. Sets MR pointer to MR1. See Figure 4-2.
RxDA 29 I Channel A receiver serial data input: The least significant bit is received first. See note on drive levels at block diagram (Figure 5-1).
RxDB 5 I Channel B receiver serial data input: The least significant bit is received first. See note on drive levels at block diagram (Figure 5-1).
TxDA 28 O Channel A transmitter serial data output: The least significant bit is transmitted first. This output is held in the Mark condition when the transmitter is disabled, Idle or when operating in local loopback mode. See note on drive levels at block diagram (Figure 5-1).
TxDB 6 O Channel B transmitter serial data output: The least significant bit is transmitted first. This output is held in the Mark condition when the transmitter is disabled, Idle, or when operating in local loopback mode. See note on drive levels at block diagram (Figure 5-1).
VCC 38, 39 Pwr Power supply: 3.3 V ± 10% or 5 V ± 10 % supply input.
WRN 3 I Write strobe: When LOW and CEN is also LOW, the contents of the data bus is loaded into the addressed register. The transfer occurs on the rising edge of the signal.
X1/CLK 30 I Crystal 1: Crystal or external clock input. A crystal or clock of the specified limits must be supplied at all times. When a crystal is used, a capacitor must be connected from this pin to ground (see Figure 4-9).
X2 31 O Crystal 2: Connection for other side of the crystal. When a crystal is used, a capacitor must be connected from this pin to ground (see Figure 4-9). If X1/CLK is driven from an external source, this pin must be left open.
Figure 3-2 68xxx Mode FR (QFP) Package
(Top View)
Table 3-2 Pin Functions for 68xxx Interface
PINS TYPE DESCRIPTION
NAME QFP (FR)
PIN NO.
A0, A1,
A2, A3		 40, 42,
44, 1		 I Address inputs: Select the DUART internal registers and ports for read/write operations.
CEN 33 I Chip enable: active LOW input signal. When LOW, data transfers between the CPU and the DUART are enabled on D0 to D7 as controlled by the WRN, RDN and A0 to A3 inputs. When HIGH, places the D0 to D7 lines in the 3-state condition.
DACKN 4 O Data transfer acknowledge. Active low output. DACKN is asserted low during a write, read, or interrupt. Acknowledge cycle to indicate data transfer between the CPU and the TL28L92.
D0, D1,
D2, D3,
D4, D5,
D6, D7		 22, 12,
21,13,
20, 14,
19, 15		 I/O Data bus: Bidirectional 3-state data bus used to transfer commands, data and status between the DUART and the CPU. D0 is the least significant bit.
GND 16, 17 Pwr Ground
IACKN 35 I Interrupt acknowledge. An active low input indicates an interrupt acknowledge cycle. Typically asserted by the CPU in response to an interrupt request. When IACKN is asserted, the TL28L92 places the interrupt vector on the bus and asserts DACKN.
IP0 2 I Input 0: General purpose input or channel A clear to send active LOW input (CTSAN).
IP1 43 I Input 1: General purpose input or channel B clear to send active LOW input (CTSBN).
IP2 34 I Input 2: General-purpose input or counter/timer external clock input.
IP3 41 I Input 3: General purpose input or channel A transmitter external clock input (TxCA). When the external clock is used by the transmitter, the transmitted data is clocked on the falling edge of the clock.
IP4 37 I Input 4: General purpose input or channel A receiver external clock input (RxCA). When the external clock is used by the receiver, the received data is sampled on the rising edge of the clock.
IP5 36 I Input 5: General purpose input or channel B transmitter external clock input (TxCB). When the external clock is used by the transmitter, the transmitted data is clocked on the falling edge of the clock.
I/M 11 I Bus configuration: When HIGH or not connected configures the bus interface to the conditions shown in this table.
INTRN 18 O Interrupt request: Active LOW, open-drain, output which signals the CPU that one or more of the eight maskable interrupting conditions are true. This pin requires a pull-up device.
N.C. 23 – Not connected
OP0 27 O Output 0: General purpose output or channel A request to send (RTSAN, active LOW). Can be deactivated automatically on receive or transmit.
OP1 7 O Output 1: General-purpose output or channel B request to send (RTSBN, active LOW). Can be deactivated automatically on receive or transmit.
OP2 26 O Output 2: General purpose output, or channel A transmitter 1× or 16× clock output, or channel A receiver 1× clock output.
OP3 8 O Output 3: General purpose output or open-drain, active LOW counter/timer output or channel B transmitter 1× clock output, or channel B receiver 1× clock output.
OP4 25 O Output 4: General purpose output or channel A open-drain, active LOW, RxA interrupt ISR[1] output.
OP5 9 O Output 5: General-purpose output or channel B open-drain, active LOW, RxB interrupt ISR[5] output.
OP6 24 O Output 6: General purpose output or channel A open-drain, active LOW, TxA interrupt ISR[0] output.
OP7 10 O Output 7: General-purpose output, or channel B open-drain, active LOW, TxB interrupt ISR[4] output.
RESETN 32 I Reset. Active low. When RESETN is asserted the following registers are cleared: SRA, SRB, IMR, ISR, OPR, and OPCR. Outputs OP0 and OP7 are driven to a logic high state, the counter/timer is stopped, and channels A and B are placed in the inactive state with the TxDA and TxDB outputs in the high state.
RxDA 29 I Channel A receiver serial data input: The least significant bit is received first. See note on drive levels at block diagram (Figure 5-2).
RxDB 5 I Channel B receiver serial data input: The least significant bit is received first. See note on drive levels at block diagram (Figure 5-2).
R/WN 3 I Read/Write: Input. When CEN is low and R/WN input is high this indicates a read cycle. When CEN is low and R/WN is low this indicates a write cycle.
TxDA 28 O Channel A transmitter serial data output: The least significant bit is transmitted first. This output is held in the Mark condition when the transmitter is disabled, Idle or when operating in local loopback mode. See note on drive levels at block diagram (Figure 5-2).
TxDB 6 O Channel B transmitter serial data output: The least significant bit is transmitted first. This output is held in the Mark condition when the transmitter is disabled, Idle, or when operating in local loopback mode. See note on drive levels at block diagram (Figure 5-2).
VCC 38, 39 Pwr Power supply: 3.3 V ± 10% or 5 V ± 10 % supply input.
X1/CLK 30 I Crystal 1: Crystal or external clock input. A crystal or clock of the specified limits must be supplied at all times. When a crystal is used, a capacitor must be connected from this pin to ground (see Figure 4-9).
X2 31 O Crystal 2: Connection for other side of the crystal. When a crystal is used, a capacitor must be connected from this pin to ground (see Figure 4-9). If X1/CLK is driven from an external source, this pin must be left open.