SLLS890C August   2008  – April 2024 TL28L92

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Description
  4. 3Pin Configurations and Functions
  5. 4Electrical Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 Static Characteristics for 5V Operation
    3. 4.3 Static Characteristics for 3.3V Operation
    4. 4.4 Dynamic Characteristics for 5V Operation
    5. 4.5 Dynamic Characteristics for 3.3V Operation
    6. 4.6 Typical Performance
    7. 4.7 Timing Diagrams
    8. 4.8 Test Information
  6. 5Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
      1. 5.3.1 Data Bus Buffer
      2. 5.3.2 Operation Control
      3. 5.3.3 Interrupt Control
      4. 5.3.4 FIFO Configuration
      5. 5.3.5 68xxx Mode
      6. 5.3.6 Timing Circuits
        1. 5.3.6.1  Crystal Clock
        2. 5.3.6.2  Baud Rate Generator
        3. 5.3.6.3  Counter/Timer
        4. 5.3.6.4  Timer Mode
        5. 5.3.6.5  Counter Mode
        6. 5.3.6.6  Time-Out Mode
        7. 5.3.6.7  Time-Out Mode Caution
        8. 5.3.6.8  Communications Channels A and B
        9. 5.3.6.9  Input Port
        10. 5.3.6.10 Output Port
      7. 5.3.7 Operation
        1. 5.3.7.1 Transmitter
        2. 5.3.7.2 Receiver
        3. 5.3.7.3 Transmitter Reset and Disable
        4. 5.3.7.4 Receiver FIFO
        5. 5.3.7.5 Receiver Status Bits
        6. 5.3.7.6 Receiver Reset and Disable
        7. 5.3.7.7 Watchdog
        8. 5.3.7.8 Receiver Time-Out Mode
        9. 5.3.7.9 Time-Out Mode Caution
  7. 6Programming
    1. 6.1 Register Overview
    2. 6.2 Condensed Register Bit Formats
    3. 6.3 Register Descriptions
      1. 6.3.1  Mode Registers
        1. 6.3.1.1 Mode Register 0 Channel A (MR0A)
        2. 6.3.1.2 Mode Register 1 Channel A (MR1A)
        3. 6.3.1.3 Mode Register 2 Channel A (MR2A)
        4. 6.3.1.4 Mode Register 0 Channel B (MR0B)
        5. 6.3.1.5 Mode Register 1 Channel B (MR1B)
        6. 6.3.1.6 Mode Register 2 Channel B (MR2B)
      2. 6.3.2  Clock Select Registers
        1. 6.3.2.1 Clock Select Register Channel A (CSRA)
        2. 6.3.2.2 Clock Select Register Channel B (CSRB)
      3. 6.3.3  Command Registers
        1. 6.3.3.1 Command Register Channel A (CRA)
        2. 6.3.3.2 Command Register Channel B (CRB)
      4. 6.3.4  Status Registers
        1. 6.3.4.1 Status Register Channel A (SRA)
        2. 6.3.4.2 Status Register Channel B (SRB)
      5. 6.3.5  Output Configuration Control Register (OPCR)
      6. 6.3.6  Set Output Port Bits Register (SOPR)
      7. 6.3.7  Reset Output Port Bits Register (ROPR)
      8. 6.3.8  Output Port Register (OPR)
      9. 6.3.9  Auxiliary Control Register (ACR)
      10. 6.3.10 Input Port Change Register (IPCR)
      11. 6.3.11 Interrupt Status Register (ISR)
      12. 6.3.12 Interrupt Mask Register (IMR)
      13. 6.3.13 Interrupt Vector Register (IVR; 68xxx Mode) or General Purpose Register (GP; 80xxx Mode)
      14. 6.3.14 Counter and Timer Registers
    4. 6.4 Output Port Notes
    5. 6.5 CTS, RTS, CTS Enable Tx Signals
  8. 7Device and Documentation Support
    1. 7.1 Receiving Notification of Documentation Updates
    2. 7.2 Support Resources
    3. 7.3 Trademarks
    4. 7.4 Electrostatic Discharge Caution
    5. 7.5 Glossary
  9. 8Revision History
  10. 9Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.3.1 Command Register Channel A (CRA)

CRA is a register used to supply commands to channel A. Multiple commands can be specified in a single write to CRA as long as the commands are non-conflicting, e.g., the enable transmitter and reset transmitter commands cannot be specified in a single command word.

Table 6-36 Command Register Channel A (CRA) (Address 0x2) Bit Description
BIT(S)SYMBOLDESCRIPTION
7 to 4–Miscellaneous commands. Execution of the commands in the upper four bits of this register must be separated by 3 X1 clock edges. Other reads or writes (including writes to the lower four bits) may be inserted to achieve this separation. A description of miscellaneous commands is given in Table 6-37.
3–Disable channel A transmitter. This command terminates transmitter operation and reset the TxDRY and TxEMT status bits. However, if a character is being transmitted or if a character is in the Tx FIFO when the transmitter is disabled, the transmission of the character(s) is completed before assuming the inactive state
2–Enable channel A transmitter. Enables operation of the channel A transmitter. The TxRDY and TxEMT status bits is asserted if the transmitter is idle
1–Disable channel A receiver. This command terminates operation of the receiver immediately-a character being received is lost. The command has no effect on the receiver status bits or any other control registers.
0–Enable channel A receiver. Enables operation of the channel A receiver. If not in the special wake-up mode, this also forces the receiver into the search for start-bit state
Table 6-37 Miscellaneous Commands
COMMANDDESCRIPTION
0000No command.
0001Reset MR pointer. Causes the channel A MR pointer to point to MR1.
0010Reset receiver. Resets the channel A receiver as if a hardware reset had been applied. The receiver is disabled and the FIFO is flushed.
0011Reset transmitter. Resets the channel A transmitter as if a hardware reset had been applied.
0100Reset error status. Clears the channel A received break, parity error, and overrun error bits in the status register (SRA[7:4]). Used in character mode to clear OE status (although RB, PE and FE bits will also be cleared) and in block mode to clear all error status after a block of data has been received.
0101Reset channel A break change interrupt. Causes the channel A break detect change bit in the interrupt status register (ISR[2]) to be cleared to zero.
0110Start break. Forces the TxDA output LOW (spacing). If the transmitter is empty the start of the break condition is delayed up to two bit times. If the transmitter is active the break begins when transmission of the character is completed. If a character is in the Tx FIFO, the start of the break is delayed until that character, or any other loaded subsequently are transmitted. The transmitter must be enabled for this command to be accepted.
0111Stop break. The TxDA line will go HIGH (marking) within two bit times. TxDA will remain HIGH for one bit time before the next character, if any, is transmitted.
1000Assert RTSN. Causes the RTSN output to be asserted (LOW).
1001Negate RTSN. Causes the RTSN output to be negated (HIGH).
1010Set time-out mode on. The receiver in this channel will restart the C/T as each receive character is transferred from the shift register to the Rx FIFO. The C/T is placed in the counter mode, the start counter or stop counter commands are disabled, the counter is stopped, and the counter ready bit, ISR[3], is reset. (see also watchdog timer description in the receiver Section 5.3.7.7.)
1011Set MR pointer to 0x0.
1100Disable time-out mode. This command returns control of the C/T to the regular start counter or stop counter commands. It does not stop the counter, or clear any pending interrupts. After disabling the time-out mode, a stop counter command should be issued to force a reset of the ISR[3] bit.
1101Not used.
1110Power-down mode on. In this mode, the DUART oscillator is stopped and all functions requiring this clock are suspended. The execution of commands other than disable Power-down mode (1111) requires a X1/CLK. While in the Power-down mode, do not issue any commands to the CR except the disable Power-down mode command. The contents of all registers is saved while in this mode. It is recommended that the transmitter and receiver be disabled prior to placing the DUART into Power-down mode. This command is in CRA only.
1111Disable Power-down mode. This command restarts the oscillator. After invoking this command, wait for the oscillator to start up before writing further commands to the CR. This command is in CRA only. For maximum power reduction input pins should be at VSS or VDD.