SLLS890C August   2008  – April 2024 TL28L92

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Description
  4. 3Pin Configurations and Functions
  5. 4Electrical Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 Static Characteristics for 5V Operation
    3. 4.3 Static Characteristics for 3.3V Operation
    4. 4.4 Dynamic Characteristics for 5V Operation
    5. 4.5 Dynamic Characteristics for 3.3V Operation
    6. 4.6 Typical Performance
    7. 4.7 Timing Diagrams
    8. 4.8 Test Information
  6. 5Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
      1. 5.3.1 Data Bus Buffer
      2. 5.3.2 Operation Control
      3. 5.3.3 Interrupt Control
      4. 5.3.4 FIFO Configuration
      5. 5.3.5 68xxx Mode
      6. 5.3.6 Timing Circuits
        1. 5.3.6.1  Crystal Clock
        2. 5.3.6.2  Baud Rate Generator
        3. 5.3.6.3  Counter/Timer
        4. 5.3.6.4  Timer Mode
        5. 5.3.6.5  Counter Mode
        6. 5.3.6.6  Time-Out Mode
        7. 5.3.6.7  Time-Out Mode Caution
        8. 5.3.6.8  Communications Channels A and B
        9. 5.3.6.9  Input Port
        10. 5.3.6.10 Output Port
      7. 5.3.7 Operation
        1. 5.3.7.1 Transmitter
        2. 5.3.7.2 Receiver
        3. 5.3.7.3 Transmitter Reset and Disable
        4. 5.3.7.4 Receiver FIFO
        5. 5.3.7.5 Receiver Status Bits
        6. 5.3.7.6 Receiver Reset and Disable
        7. 5.3.7.7 Watchdog
        8. 5.3.7.8 Receiver Time-Out Mode
        9. 5.3.7.9 Time-Out Mode Caution
  7. 6Programming
    1. 6.1 Register Overview
    2. 6.2 Condensed Register Bit Formats
    3. 6.3 Register Descriptions
      1. 6.3.1  Mode Registers
        1. 6.3.1.1 Mode Register 0 Channel A (MR0A)
        2. 6.3.1.2 Mode Register 1 Channel A (MR1A)
        3. 6.3.1.3 Mode Register 2 Channel A (MR2A)
        4. 6.3.1.4 Mode Register 0 Channel B (MR0B)
        5. 6.3.1.5 Mode Register 1 Channel B (MR1B)
        6. 6.3.1.6 Mode Register 2 Channel B (MR2B)
      2. 6.3.2  Clock Select Registers
        1. 6.3.2.1 Clock Select Register Channel A (CSRA)
        2. 6.3.2.2 Clock Select Register Channel B (CSRB)
      3. 6.3.3  Command Registers
        1. 6.3.3.1 Command Register Channel A (CRA)
        2. 6.3.3.2 Command Register Channel B (CRB)
      4. 6.3.4  Status Registers
        1. 6.3.4.1 Status Register Channel A (SRA)
        2. 6.3.4.2 Status Register Channel B (SRB)
      5. 6.3.5  Output Configuration Control Register (OPCR)
      6. 6.3.6  Set Output Port Bits Register (SOPR)
      7. 6.3.7  Reset Output Port Bits Register (ROPR)
      8. 6.3.8  Output Port Register (OPR)
      9. 6.3.9  Auxiliary Control Register (ACR)
      10. 6.3.10 Input Port Change Register (IPCR)
      11. 6.3.11 Interrupt Status Register (ISR)
      12. 6.3.12 Interrupt Mask Register (IMR)
      13. 6.3.13 Interrupt Vector Register (IVR; 68xxx Mode) or General Purpose Register (GP; 80xxx Mode)
      14. 6.3.14 Counter and Timer Registers
    4. 6.4 Output Port Notes
    5. 6.5 CTS, RTS, CTS Enable Tx Signals
  8. 7Device and Documentation Support
    1. 7.1 Receiving Notification of Documentation Updates
    2. 7.2 Support Resources
    3. 7.3 Trademarks
    4. 7.4 Electrostatic Discharge Caution
    5. 7.5 Glossary
  9. 8Revision History
  10. 9Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4.4 Dynamic Characteristics for 5V Operation

over operating free-air temperature range (unless otherwise noted) (1)(2)(3)(4)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
Reset Timing (see Figure 4-2)
tRESReset pulse width10018ns
Bus Timing(5) (see Figure 4-3)
tASA0 to A3 set-up time to RDN, WRN LOW106ns
tAHA0 to A3 hold time from RDN, WRN LOW2012ns
tCSCEN set-up time to RDN, WRN LOW0ns
tCHCEN hold time from RDN, WRN LOW0ns
tRWWRN, RDN pulse width (LOW time)158ns
tDDData valid after RDN LOW125 pF load; see Figure 4-1 for smaller loads4055ns
tDARDN LOW to data bus active0(6)ns
tDFdata bus floating after RDN or CEN HIGH20ns
tDIRDN or CEN HIGH to data bus invalid0ns
tDSData bus set-up time before WRN or CEN HIGH (write cycle)2517ns
tDHData hold time after WRN HIGH0–12ns
tRWDHIGH time between read and/or write cycles1710ns
Port Timing(5) (see Figure 4-7)ns
tPSPort in set-up time before RDN LOW
(Read IP ports cycle)		0–20ns
tPHPort in hold time after RDN HIGH0–20
tPDOP port valid after WRN or CEN HIGH
(OPR write cycle)		4060
Interrupt Timing (see Figure 4-8)
tIRINTRN (or OP3 to OP7 when used as interrupts)Read Rx FIFO
(RxRDY/FFULL interrupt)		4060ns
Write Tx FIFO
(TxRDY interrupt)		4060
Reset command
(delta break change interrupt)		4060
Stop C/T command
(counter/timer interrupt)		4060
Read IPCR
(delta input port change interrupt)		4060
Write IMR
(clear of change interrupt mask bit(s))		4060
Clock Timing (see Figure 4-9)
tCLKX1/CLK HIGH or LOW time3020ns
fCLKX1/CLK frequency0.1(7)3.6868MHz
tCTCC/T clock (IP2) HIGH or LOW time
(C/T external clock input)		3010
fCTCC/T clock (IP2) frequency0(7)8MHz
tRXRxC HIGH or LOW time16×3010ns
fRXRxC frequency16×0(7)16MHz
1×(8)0(7)1
tTXTxC HIGH or LOW time16×3010ns
fTXTxC frequency16×16MHz
1×(8)0(8)1
Transmitter Timing, External Clock (see Figure 4-10)
tTXDTxD output delay from TxC LOW (TxC input pin)4060ns
tTCSOutput delay from TxC output pin LOW to TxD data output630ns
Receiver Timing, External Clock (see Figure 4-11)
tRXSRxD data set-up time to RxC HIGH5040ns
tRXHRxD data hold time from RxC HIGH5040ns
68xxx or Motorola Bus Timing (see Figure 4-3, Figure 4-4, and Figure 4-5)(9)
tDCRDACKN LOW (read cycle) from X1 HIGH1535ns
tDCWDACKN LOW (write cycle) from X1 HIGH1535ns
tDATDACKN high-impedance from CEN or IACKN HIGH810ns
tCSCCEN or IACKN set-up time to X1 HIGH for minimum DACKN cycle168ns
(1) Parameters are valid over specified temperature and voltage range.
(2) All voltage measurements are referenced to ground. For testing, all inputs swing between 0.4V and 3V with a transition time of 5ns maximum. For X1/CLK this swing is between 0.4V and 0.8 × VCC. All time measurements are referenced at input voltages of 0.8V and 2V, and output voltages of 0.8V and 2V, as appropriate.
(3) Test conditions for outputs: CL = 125pF, except open-drain outputs. Test conditions for open-drain outputs: CL = 125pF, constant current source = 2.6mA.
(4) Typical values are the average values at 25°C and 5V.
(5) Timing is illustrated and referenced to the WRN and RDN Inputs. Also, CEN may be the strobing input. CEN and RDN (also CEN and WRN) are ORed internally. The signal asserted last initiates the cycle and the signal negated first terminates the cycle.
(6) Specified by characterization of sample units.
(7) Minimum frequencies are not tested but are specified by design.
(8) Clocks for 1× mode should maintain a 60/40 duty cycle or better.
(9) Minimum DACKN time is ((tDCR or tDCW) tCSC + 2 X1 edges + rise time over 5ns). Two X1 edges is 273ns at 3.6864MHz. For faster bus cycles, the 80xxx bus timing may be used while in the 68xxx mode. It is not necessary to wait for DACKN to insure the proper operation of the SC28C92. In all cases, the data is written to the TL28L92 on the falling edge of DACKN or the rise of CEN. The fall of CEN initializes the bus cycle. The rise of CEN ends the bus cycle. DACKN LOW or CEN HIGH completes the write cycle.