SLLS890C August 2008 – April 2024 TL28L92
PRODUCTION DATA
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|
RxRTS control | RxINT[1] | ERRORMODE | PARITY MODE | PARITY TYPE | bits per character |
BIT(S) | SYMBOL | DESCRIPTION |
---|---|---|
7 | RxRTS | Channel A receiver request to send control (flow control). This bit controls the deactivation of the RTSAN output (OP0) by the receiver. This output is normally asserted by setting OPR[0] and negated by resetting OPR[0]. Proper automatic operation of flow control requires OPR[0] (channel A) or OPR[1] (channel B) to be set to logic 1. 0 = No RTS control 1 = RTS control RxRTS = 1 causes RTSAN to be negated (OP0 is driven to a logic 1 [VCC]) upon receipt of a valid start bit if the channel A FIFO is full. This is the beginning of the reception of the 9th byte. If the FIFO is not read before the start of the 10th or 17th byte, an overrun condition will occur and the 10th or 17th or 17th byte is lost. However, the bit in OPR[0] is not reset and RTSAN is asserted again when an empty FIFO position is available. This feature can be used for flow control to prevent overrun in the receiver by using the RTSAN output signal to control the CTSN input of the transmitting device. |
6 | RxINT[1] | Bit 1 of the receiver interrupt control. See description of RxINT[2] in Table 6-22 and Table 6-23. |
5 | ERRORMODE | Channel A error mode select. 0 = character 1 = block This bit selects the operating mode of the three FIFOed status bits (FE, PE, received break) for channel A. In the character mode, status is provided on a character-by-character basis; the status applies only to the character at the top of the FIFO. In the block mode, the status provided in the SR for these bits is the accumulation (logic OR) of the status for all characters coming to the top of the FIFO since the last reset error command for channel A was issued. |
4 and 3 | PARITY MODE | Channel A parity mode select 00 = with parity 01 = force parity 10 = no parity 11 = multi-drop special mode |
2 | PARITY TYPE | Channel A parity type select 0 = even 1 = odd This bit selects the parity type (odd or even) if the with parity mode is programmed by MR1A[4:3], and the polarity of the forced parity bit if the force parity mode is programmed. |
1:0 | – | Channel A bits per character select. 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits This field selects the number of data bits per character to be transmitted and received. The character length does not include the start, parity, and stop bits. |