SGLS380I September   2008  – May 2024 TL720M05-Q1

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Undervoltage Lockout
      2. 7.3.2 Thermal Shutdown
      3. 7.3.3 Current Limit
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Input and Output Capacitor Selection
        1. 8.1.1.1 Legacy Chip Capacitor Selection
        2. 8.1.1.2 New Chip Output Capacitor
        3. 8.1.1.3 New Chip Input Capacitor
      2. 8.1.2 Dropout Voltage
      3. 8.1.3 Reverse Current
      4. 8.1.4 Power Dissipation (PD)
        1. 8.1.4.1 Thermal Performance Versus Copper Area
        2. 8.1.4.2 Power Dissipation Versus Ambient Temperature
      5. 8.1.5 Estimating Junction Temperature
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Capacitor
        2. 8.2.2.2 Output Capacitor
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Examples
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Evaluation Module
      2. 9.1.2 Device Nomenclature
      3. 9.1.3 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • KVU|3
  • PWP|20
  • KTT|3
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.1.4.1 Thermal Performance Versus Copper Area

The most used thermal resistance parameter RθJA is highly dependent on the heat-spreading capability built into the particular PCB design. Therefore, RθJA varies according to the total copper area, copper weight, and location of the planes. The RθJA recorded in the Thermal Information table is determined by the JEDEC standard (see Figure 8-1), PCB, and copper-spreading area. RθJA is only used as a relative measure of package thermal performance. For a well-designed thermal layout, RθJA is actually the sum of RθJCbot plus the thermal resistance contribution by the PCB copper. RθJCbot is the package junction-to-case (bottom) thermal resistance.

TL720M05-Q1 JEDEC Standard 2s2p PCBFigure 8-1 JEDEC Standard 2s2p PCB

Figure 8-2 and Figure 8-3 show the functions of RθJA and ψJB versus copper area and thickness. These plots are generated with a 101.6mm × 101.6mm × 1.6mm PCB of two and four layers. For the 4-layer board, inner planes use 1oz copper thickness. Outer layers are simulated with both 1oz and 2oz copper thickness. A 3×4 (KVU package) array of thermal vias with a 300µm drill diameter and 25µm copper plating is located beneath the device thermal pad. The thermal vias connect the top layer, the bottom layer and, in the case of the 4-layer board, the first inner GND plane. Each of the layers has a copper plane of equal area.

TL720M05-Q1 RθJA vs Copper Area (KVU Package)Figure 8-2 RθJA vs Copper Area (KVU Package)
TL720M05-Q1 ψJB vs Copper Area (KVU Package)Figure 8-3 ψJB vs Copper Area (KVU Package)